Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2002-01-08
2003-12-02
Shingleton, Michael B (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S034000, C331S016000, C331S1170FE
Reexamination Certificate
active
06657500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of simplified representations of electronic circuits to model responses of the electronic circuits to input stimuli. More particularly this invention relates to the simplified representations of circuits such as phase-locked loops to efficiently predict the behavior of the circuits to input stimuli.
2. Description of Related Art
Today, there are new mixed-signal and multi-level simulation languages, which can accurately represent the analog portion of the mixed circuits with behavioral models. Behavioral models are “if-then-else” structured programs, which describe the analog circuit's behavior. The “if-then-else” structured program is based on the basis that an input signal to a known system will produce a predictable response signal. Thus, if a function for the input signal vs. output signal is derived, the behavior of the circuit can be predicted without having a full circuit or device level model. The function may be a simple table lookup of input signal levels with attendant response signal levels or a complex mathematical function having multiple parameters of the input signal necessary to derive the output response.
FIG. 1
shows a system diagram for a phase-locked loop (PLL). A PLL circuit causes a given system to track with another system. A PLL typically causes one electrical signal with a given frequency to track, follow, or become synchronized with another electrical signal. In
FIG. 1
, the PLL synchronizes a Voltage Controlled Oscillator (VCO
185
) signal with a reference signal (Vref
180
). The PLL synchronizes frequency as well as phase. When Vref and VCO are synchronized, the PLL is in a “locked” state. In this state, the phase error between VCO and Vref is zero or close to zero. If a finite phase error builds up, the PLL circuit in
FIG. 1
uses a feedback control mechanism, which causes the phase error to approach, zero once again.
The phase frequency detector
120
compares the phase of VCO to Vref and produces an output signal, which is proportional to the phase error. This output signal has AC and DC components. In
FIG. 1
, the loop filter
150
, which is usually a first-order low-pass filter, filters out the AC component. The voltage controlled oscillator (VCO) produces an output signal, which has a frequency, which is a function of the VCO input, which is the control voltage.
FIG. 2
shows a standard VCO transfer function where the output signal frequency is plotted vs. the VCO input control voltage. The divider circuit
170
in
FIG. 1
is an option, which is needed only when the VCO output frequency is a multiple N times greater than the frequency of Vref. In this case, the divider would be a Divide-by-N circuit. Similarly, the divider in
FIG. 1
could be replaced by a multiplier if the VCO output frequency is a multiple N times less than the frequency of Vref. In order for the phase frequency detector
120
to work, the frequencies of Vref and VCO must be close to each other. The charge pump circuit
140
in
FIG. 1
takes the up/down voltage output of the phase frequency detector
120
and outputs a proportional current which goes to the loop filter
150
. A state diagram in
FIG. 3
a
shows the three states of the phase frequency detector
120
and the three phase detector output voltage states which control the action of the charge pump circuit
140
. The phase angle diagram in
FIG. 3
b
shows two counterclockwise rotating vectors, which represent the VCO and Vref signals. The input control for the state diagram in
FIG. 3
a
can be understood by following the two rotating vectors as they rotated past the trigger axis shown in
FIG. 3
b
. This mechanism is the feedback control system, which causes the VCO signal to “lock on to”, the Vref signal after several oscillation cycles via the charge pump current source/sink function of
FIG. 3
a
. The speed of reaching the equilibrium state of “locking on to” the Vref signal by the VCO signal is a figure of merit of phase locked loops.
Simulation of the PLL blocks described consists of the following models. The phase frequency detector is modeled as a behavioral model with two inputs, VCO and Vref. The model determines the lead-lag relationship and the frequency/phase difference. It then delivers two signals to direct the charge pump circuitry to source current, sink current or turn the charge pump current off.
A state machine similar to
FIG. 3
a
is included in the phase frequency detector model. The current and voltage values used in the behavioral model tables are obtained from simulation of computer aided circuit design models. The VCO
185
is modeled as a behavioral model. Circuit simulation provides the output frequency vs. control voltage transfer curve, such as in FIG.
5
. The charge pump
140
is modeled with a behavioral where the relationship between the output voltage and pump current is modeled with tables, which were constructed from circuit analysis results. The divider
170
in
FIG. 1
is basically a counter that outputs a clock signal whose frequency in the input clock divided or multiplied by a parameter, N. The voltage relationship between input and output signals is derived from circuit analysis and can be described with digital event-driven behavioral statements. Finally, the loop filter
150
in
FIG. 1
is modeled as an RC low-pass network where each component is represented by an analytical I-V transfer function.
U.S. Pat. No. 5,392,227 (Hiserote) provides a system and a method for translating gate level design data into behavioral level simulation models that are accurate and have high simulation performance. It also provides accurate simulation models for complex integrated circuits prior to the availability of the circuits.
U.S. Pat. No. 5,987,238 (Chen) provides a method for making a phase-locked loop circuit. The method includes a method of simulating the phase-locked loop circuit.
Smedt et al., “Models for Systematic Design and Verification of Frequency Synthesizers,” IEEE Transactions on Circuit and Systems—II: Analog and Digital Signal Processing, Vol. 46, No. 10, October 1999, IEEE, provides models for the design and verification of frequency synthesizers. It provides for insight into both the top-down high level design and the bottom-up low-level verification phase of frequency synthesizer development.
BRIEF SUMMARY OF THE INVENTION
It is an object of this invention to provide a piecewise linear phase locked loop frequency generator to generate a voltage signal controlled by an input voltage.
In addition, it is also an objective of this invention to provide a model of a phase locked loop to be simulated within a simulator to determine the function of a phase locked loop within an electronic system.
These and other objects of this invention are accomplished by a piecewise linear phase locked loop frequency generator. The piecewise linear phase locked loop frequency generator has a variable static frequency generator, whose frequency is selected by a control voltage and whose transfer function between control voltage and output frequency is further selected by a frequency selection parameter, n. This frequency selection parameter, n, designates the number, which identifies which portion of the frequency spectrum is being represented by the control voltage to frequency transfer function being selected. Second, a set of low pass filters is used to work in conjunction with the corresponding control voltage to output frequency transfer functions, which are selected by a frequency selection parameter, n. The number of low pass filters is equal to the frequency selection parameter n. Finally, a switch circuit is employed to select as a function of the frequency selection parameter, n, which low pass filter output should be presented as the dynamic frequency which corresponds to the original control voltage input.
The simulation model would use the behavioral model of a variable static frequency generator. The frequency of the variable static fuse generator is selected by
Ackerman Stephen B.
Knowles Billy
Saile George O.
Shingleton Michael B
Taiwan Semiconductor Manufacturing Company
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