Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-09-26
2003-12-09
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S778000, C257S734000, C257S737000, C257S738000, C257S784000, C257S785000
Reexamination Certificate
active
06661088
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-273215, filed Sep. 27, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having an interposer and a method of manufacturing the same.
As a semiconductor integrated circuit chip (hereinafter, referred to as “LSI chip”) is reduced in size and integrated more and more, the number of pads formed of the uppermost wiring layer has been increased. Furthermore, with the increase in number, it has been accelerated that the pads are arranged at fine (narrow) intervals (hereinafter, called “pitches”).
With this tendency of fine arrangement of the pads on the LSI chip, it is required for the wiring layers to be arranged at fine pitches on a package substrate, on which the LSI chip is to be mounted. However, if the wiring layers are arranged at fine pitches on the package substrate, the manufacturing cost of the package substrate increases. Therefore, even though the manufacturing cost per LSI chip is reduced by virtue of the miniaturization of the LSI chip, the manufacturing cost of the package substrate increases, increasing the total manufacturing cost of an LSI product formed of the LSI chip and the package substrate.
In the circumstances, an attempt has been made to place a member in the space between the LSI chip and the package substrate, for rearranging the pads which are arranged at fine pitches, to rough (wider) pitches, while the wiring layers are arranged at the rough pitches on the package substrate. The member is called an interposer which is responsible for rearranging the pads arranged at fine pitches on the LSI chip, at wider pitches. If the interposer is placed between the LSI chip and the package substrate, the cost of the package substrate can be maintained at the same level as that of a conventional one. Therefore, the manufacturing cost of the LSI product, which is formed of the LSI chip, interposer and package substrate, can be reduced.
On the other hand, as the width of the wiring layer within the LSI chip is reduced, the performance of the wiring layer decreases, with the result that the RC delay significantly occurs. In addition, with the miniaturization of the wiring layer itself, the deterioration in reliability of the LSI product is significantly observed. In future, as a wiring material, copper is going to be used in place of aluminum. As the interlayer insulating film, a material having a low dielectric constant is going to be inevitably employed.
However, as the wiring material changes and a material having a low dielectric constant is going to be used as the interlayer insulating film, new equipment has to be introduced, raising the manufacturing cost.
Furthermore, the number of wiring layers within the LSI chip has increased year after year, and thereby, the wiring formation steps increase. If the number of the wiring formation steps increases, not only the yield but also the throughput decreases, lowering the productivity in a plant.
In these circumstances, the manufacturing cost of the LSI chip itself has been rapidly increasing.
BRIEF SUMMARY OF THE INVENTION
The present invention is made in the aforementioned circumstances. An object of the present invention is to provide a semiconductor integrated circuit device which is formed of a semiconductor integrated circuit chip and a package substrate, the chip being mounted on the package substrate, and which is capable of suppressing an increase of a manufacturing cost, and also to provide a method of manufacturing the semiconductor integrated circuit device.
To attain the object, according to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
a semiconductor chip having a plurality of first pads arranged at first pitches on a surface thereof;
an interposer having a first surface and a second surface, said first surface having a plurality of second pads arranged at the first pitches thereon and said second surface having a plurality of third pads arranged at second pitches which are larger than the first pitches; and
a substrate having a plurality of fourth pads arranged at the second pitches on a surface thereof, wherein
the second pads and the first pads are connected to each other by joining the first surface of the interposer to the surface of the semiconductor chip so as to face each other; and
the fourth pads and the third pads are connected to each other by joining the surface of the substrate to the second surface of the interposer so as to face each other.
According to the semiconductor integrated circuit device having the aforementioned structure, the fourth pads can be arranged on the substrate at second pitches which are larger than the first pitches at which the first pads are arranged on the semiconductor chip. Therefore, it is possible to use an inexpensive substrate material and thereby prevent an increase of the manufacturing cost of the semiconductor integrated circuit device.
To attain the aforementioned object, according to a second aspect of the present invention, there is provided a semiconductor integrated circuit device having a first circuit and a second circuit, comprising:
a semiconductor chip having the first circuit formed therein;
an interposer having the second circuit formed therein, said semiconductor chip being mounted on the interposer; and
a substrate on which the interposer is to be mounted.
According to the semiconductor integrated circuit device having the aforementioned structure, at least a part of the circuits formed in the semiconductor integrated circuit device is formed in the interposer. It is therefore possible to prevent an increase of the number of wiring layers of the semiconductor chip. As a result, it is possible to prevent a decrease of the yield due to the increase of the number of wiring layers. Furthermore, it is possible to prevent deterioration of the throughput due to the increase of the number of manufacturing steps. It follows that the semiconductor integrated circuit device can be prevented from increasing in manufacturing cost.
To attain the aforementioned object, according to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
forming a first substrate having a cell transistor and a plug connected to a source or a drain of the cell transistor, said plug having a site exposed outside;
forming a second substrate having a storage node electrode, a plate electrode and a ferroelectric film; said storage node electrode having a site exposed outside and said ferroelectric film being sandwiched between the plate electrode and the storage node electrode; and
forming a ferroelectric RAM memory cell formed of a stacked structure of the first substrate and the second substrate by connecting the site of the plug exposed outside and the site of the storage node electrode exposed outside to each other.
To attain the aforementioned object, according to a fourth aspect of the present invention, there is provided comprising the steps of:
forming a first substrate having a cell transistor and a plug connected to a source or a drain of the cell transistor, said plug having a site exposed outside;
forming a second substrate having a storage node electrode, a plate electrode and a ferroelectric film; said storage node electrode having a site exposed outside, and said ferroelectric film being sandwiched between the plate electrode and the storage node electrode; and
forming a magnetic RAM memory cell formed of a stacked structure of the first substrate and the second substrate by connecting the site of the plug exposed outside and the site of the storage node electrode exposed outside to each other.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious f
Ezawa Hirokazu
Yoda Takashi
Abraham Fetsum
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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