Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Patent
1997-05-09
1999-10-26
Eng, David Y.
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
G06F 900
Patent
active
059745355
ABSTRACT:
A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.
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Gurindar Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiplt Functional Unit, Pipelined Computers, IEEE Transactions On Computers, vol. 39, No. 3 pp. 349-359, Mar. 1990.
Chow Daniel Chen
Peng Chih-Jui Ray
Potter Terence Matthew
Rossbach Paul Charles
Dillon Andrew J.
Eng David Y.
International Business Machines - Corporation
Salys Casimer K.
Yociss Lisa B.
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