Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
1998-12-29
2002-01-08
Ellis, Richard L. (Department: 2783)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
Reexamination Certificate
active
06338134
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems, and in particular to the efficient processing of one of multiple instructions to be processed during a single clock cycle in a superscalar data processing system by moving only pointers to data. Still more particularly, the present invention relates to a method and system in a superscalar data processing system for efficiently processing an instruction which specifies data to be moved from a logical origination location to a logical destination location by moving a pointer to the data into a field associated with the instruction and the destination location, wherein the data remains in its original location.
2. Description of the Related Art
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required. Instructions are first fetched and then decoded. The overlap of the fetching and decoding of one instruction with the execution of a second instruction is called pipelining. In pipelined superscalar data processing systems, care must be taken to avoid dependencies where multiple instructions are fetched, decoded, and executed in a single cycle.
Software, written to load, store, and perform other operations, utilizes logical register names. These logical register names identify particular general registers. Typically, there are eight general registers which may be identified by software. In known systems, general purpose architectural registers, also called general registers, exist separate and apart from other registers which may also be included, such as special purpose registers, and rename registers. These general registers are initially associated with a particular logical register name.
For example, one of the general purpose registers may be designated as general register
2
and be associated with a logical register name of “2”. A typical software instruction may attempt to load data into general register
2
. This instruction may be written: LOAD
2
, data
1
. When processing this instruction, a copy of the data stored in storage location data
1
will be loaded into the general register designated as general register
2
. In such systems, any time an instruction is associated with a logical register name of “2”, it will utilize the general register designated as general register
2
.
Each general register included in these systems is designated as a particular general register. Often there may be eight general registers in a system. In this case, the general registers may be designated as general register
1
through general register
8
. These general register designations exist in hardware and are therefore determined prior to the system ever being powered on. These designations never change. A general register designated as general register
1
will always be designated as general register
1
. Further, no other register can ever be designated as general register
1
.
In superscalar data processing systems, one potential conflict may arise when multiple instructions are to be processed during a single clock cycle. A conflict may exist when two or more of these instructions attempt to utilize the same general register. For example, the following instruction sequence may need to be concurrently processed:
Instruction N
1
: LOAD
2
, data
1
Instruction N
2
: ADD REG
2
,
3
Instruction N
3
: STORE
2
, temp
Instruction N
4
: LOAD
2
, data
2
A conflict arises during scheduling of these instructions because both instructions N
1
and N
4
load different data into general register
2
. The instructions may be scheduled such that instruction N
4
destroys the result from instruction N
2
before instruction N
3
had a chance to put the result into storage location “temp”.
Instructions may move data between a storage location and a stack location. A stack is a designated dynamic area of memory, either main memory or a cache, that stores temporary logical register information and returns addresses of subroutines. The stack includes stack registers which are the multiple, contiguous storage locations into which data may be stored. The number of stack registers may expand or contract over time by having stack registers added to or removed from the stack. The stack is addressed by a stack pointer which is the address of the top of the stack. The top of the stack is the memory location which contains the data item most recently stored in the stack during a “PUSH” operation. Typically, a stack supports two types of operations, a PUSH and a POP. A PUSH operation adds a stack register to the top of the stack. A POP operation removes a stack register from the top of the stack.
A stack is a software programming model. When this model is mapped to hardware, it is implemented in main memory and temporarily resides in a cache. Although the programmer may treat stack registers in the stack as if they are registers, the stack registers are not actual physical registers. They are either main memory or cache locations. Therefore, accessing data stored in stack registers in a stack are subject to the performance problems associated with the accessing of memory.
Data may be moved from a main memory storage location into a stack register in a stack. The memory moved into the stack may then be moved into general registers. Logical or arithmetic operations may then be performed utilizing the data stored in the general registers. The results of these operations are then moved back to main memory. Therefore, in order to process an instruction which specifies data to be moved during the processing of the instruction into or out of a stack register, the data must be moved into and out of several memory locations, in the stack, general registers, and main memory or cache.
Therefore a need exists for a method and system in a superscalar data processing system for the efficient processing of an instruction by moving pointers to data such that the data is not copied and remains in its original physical location.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide a method and system for the efficient processing of one of multiple instructions to be processed during a single clock cycle which specifies data to be moved during the processing of the instruction in a superscalar data processing system by moving only pointers to data.
It is yet another object of the present invention to provide a method and system in a superscalar data processing system for efficiently processing an instruction which specifies data to be moved from an origination location to a destination location by moving a pointer to the data into a field associated with the instruction and the destination location, wherein the data remains in its original location.
The foregoing objects are achieved as is now described. A method and system in a superscalar data processing system are disclosed for the efficient processing of an instruction by moving only pointers to data. Multiple instructions in the superscalar data processing system are processed during a single clock cycle. A determination is made whether one of these instructions is a particular type of instruction which specifies data to be moved from a logical origination location to a logical destination location during processing of the instruction. In response to a determination that the instruction is a particular type of instruction, a first pointer field is established associated with the instruction for associating a pointer stored in the first pointer field with the logical origination location. A second pointer field is also established associated with the instruction for associating a pointer stored in the second pointer field with the logical destination location. A first pointer
Harwood Frank Cassatt
Leung Wan Lin
Bracewell & Patterson LLP
Ellis Richard L.
LandOfFree
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