Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-08-21
2003-02-25
Martin, David (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S760000, C361S761000, C361S790000, C361S767000, C361S803000, C361S811000, C361S764000, C361S782000, C361S766000, C361S807000
Reexamination Certificate
active
06525945
ABSTRACT:
TECHNICAL FIELD
The invention relates to the field of decoupling capacitors for integrated circuits. More particularly, this invention relates to a capacitor arrangement suitable for wide band decoupling of a ball grid array module.
BACKGROUND ART
It is well known in the field of microelectronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit. Generally, the prevention of the coupling of undesired high frequency noise or interference into the power supply for an integrated circuit (IC) is accomplished by connecting one or more decoupling capacitors between the power and ground leads of the IC.
With the high complexity of nowadays ICs which offer a great number of input and output I/Os (up to 1,000 I/Os), it is mandatory that the I/Os be disposed in a matricial arrangement, such as the 1,024 I/Os matrix arranged as a 32 rows by 32 columns for the so-called Ball Grid Array (BGA) package. With such packaging, the distance between two adjacent balls is reduced to the order of half a millimeter such that it prevents the location of known decoupling components within such limited free area.
Hernandez et al. U.S. Pat. No. 5,422,782, the disclosure of which is incorporated by reference herein, discloses a decoupling capacitor comprising a plurality of capacitive elements arranged to form a single component which is mounted in an open area under an integrated circuit package. Such decoupling capacitor is not usable in the ball grid array structure which does not offer sufficient free space area. Moreover, the drawback of such assembled component is that the intrinsic inductance of each capacitive element is downgraded by the parasitic inductance of each corresponding conductor acting as a multi capacitive element lead.
One known scheme for decoupling in the BGA packages is to use one or more discrete capacitors which are mounted on a multilayer printed circuit board (PCB) around the integrated circuit. Plated through holes are then used to connect the capacitors to the internal power plane and ground plane, which in turn make contact with the power supply connection leads of the integrated circuit. In this connection scheme, the capacitors are mounted as close to the integrated circuit as possible to reduce the length of the trace connection paths between the capacitors plates and the IC power pins and ground pins. Indeed, trace paths have an inductance which is proportional to the paths length and that causes increased noise when the circuit is used in high speed environments. Kelly et al. U.S. Pat. No. 5,798,567, the disclosure of which is incorporated by reference herein, discloses a ball grid array integrated circuit package with power supply decoupling capacitors attached to the upper or the lower surface of the BGA directly in front of the integrated circuit in order to minimize the distance between a power supply balls of the integrated circuit and the decoupling capacitors. In this patent, various implementations of decoupling capacitors are shown mounted on a BGA. Even if these solutions provide an efficient decoupling in the high frequency regions, they require that the BGA package integrates the mounting of the decoupling capacitors which adds an overcost for the packaging.
The present invention solves the aforementioned problem at a minimum cost by mounting decoupling capacitors at the card level, i.e. on the printed circuit board.
Electronic theory recites that discrete capacitors are modeled by a parasitic inductance in series with a capacitance. Below the resonance frequency of the capacitor, the main active component is capacitive reactance while at resonance point it is equivalent series resistance, and above resonance point it is inductive reactance. Therefore, the decoupling function of a capacitor is optimum for a range of frequencies around the resonance frequency where the resulting impedance is the lowest. In order to improve the decoupling for a particular frequency region, several identical capacitors of the same value may be arranged in parallel such that the overall impedance at the resonance point can be lowered.
Recent complex integrated circuits for example such as microprocessors in the field of computers, or packet/cell switch circuits (e.g. Asynchronous Transfer Mode cell switch circuits) in the networking field, integrate on the same chip a plurality of logical functions which operate at different working frequencies. For example a networking switch circuit may include a microcontroller interface operating at 10 Mhz (Megahertz), a switch core operating at 100 Mhz, and a serializer/deserializer function operating at 400 Mhz and above.
Furthermore, due to the Fourier transform of the rising edge and the falling edge of switching signals such as clock signal (the highest frequency) or data signal, some “Fourier derived frequencies” provide undesirable additional noise. It is to be noted that such Fourier frequencies are at least five times the working frequencies.
Therefore, in the context of multi-frequencies circuits, an efficient decoupling technique should be capable of filtering a wide range of frequencies including the additional ones, e.g. from about 10 Mhz up to about 400 MHz as cited in the previous example.
A technique known in the art for decoupling an integrated circuit over a plurality of frequencies relies on using several capacitors having different capacitance values. The capacitance values generally range from a lower value to a higher value such as to provide at least a high and a low frequency filtering. However, this technique suffers from two major drawbacks. Firstly, there is always an uncertainty as to the value of the resonance frequency of commercially available discrete capacitors due to the inherent dispersion on the value of the intrinsic inductance associated with the discrete capacitor. This may lead to a value of the resonance frequency which is shifted compared to the desired frequency at which the integrated circuit must be decoupled, and thus resulting in a partly inefficient decoupling. Secondly, even if an appropriate choice of discrete capacitor gives a substantially efficicent decoupling around the discrete working frequencies of the integrated circuit, the decoupling is generally not operative over a wide range of frequencies and particularly not operative for the high frequency values caused by the above-defined “Fourier derived frequencies” as it is the case for the aforementioned patents.
Therefore, in the context of complex integrated circuits having multiple working frequencies, there is a need for a low cost decoupling technique that provides an efficient decoupling of such integrated circuits over a wide range of frequencies.
BRIEF SUMMARY OF THE INVENTION
The object of the invention is therefore to provide a decoupling method and system that addresses the foregoing need in order to solve the deficiencies of the prior art. This object is met in accordance with the invention in which an electronic package comprising a printed circuit board on which are mounted a plurality of decoupling capacitors is claimed. A carrier component electrically connects an integrated circuit to the printed circuit board through a plurality of solder balls. The plurality of solder balls comprises at least one solder ball for the integrated circuit ground voltage connection and at least one solder ball for the integrated circuit power voltage connection. The plurality of decoupling capacitors is organized as a set of “n” capacitors ranged from a lower capacitor value “C
low
” to a higher capacitor value “C
high
” such that the range C
low
to C
high
of the “n” capacitor values is a function of the frequency range F
low
to F
high
on which the integrated circuit operates.
In an embodiment, each consecutive capacitor value is a function of the previous capacitor value according to a multiplying factor of
R
=
K
1
n
-
1
where
K
=
(
F
High
F
Low
)
2
·
In one aspect, the method of suppressing noise in the electronic
Louis Philippe Pierre
Michel Patrick
Verhaeghe Michel Paul
Blecker Ira D.
International Business Machines - Corporation
Martin David
Tran Thanh Y.
LandOfFree
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