Method and system for wafer lot order

Details Method and system for wafer lot order Method and system for wafer lot order

2007-02-13

2009-10-27

Shechtman, Sean P (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S100000, C700S103000, C700S108000, C700S121000

Reexamination Certificate

active

07610111

ABSTRACT:
Methods and systems for wafer lot ordering using including estimation of allowable queue time based on utilization loss and rework percentage have been achieved. The method invented comprises steps of ranking lots, allocating equipment to the exit step of queue time, calculating and determining the optimal allowable queue time based on utilization loss and rework percentage, calculating the next available time for equipment, calculating earliest release time, and releasing lot/batch and pre-assign it to the equipment at exit step. The present invention can be applied to other manufacturing lines than semiconductor manufacturing.

REFERENCES:
patent: 5818716 (1998-10-01), Chin et al.
patent: 5841677 (1998-11-01), Yang et al.
patent: 6470231 (2002-10-01), Yang et al.
patent: 6763277 (2004-07-01), Allen, Jr. et al.
patent: 6941183 (2005-09-01), Huang et al.
patent: 7020594 (2006-03-01), Chacon
patent: 7027885 (2006-04-01), Barto et al.
patent: 7151972 (2006-12-01), Denton et al.
patent: 2005/0234578 (2005-10-01), Liu et al.

Affiliated with

Also associated with

Rating

Method and system for wafer lot order does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for wafer lot order, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for wafer lot order will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4076231