Method and system for verification of soft error handling...

Details Method and system for verification of soft error handling... Method and system for verification of soft error handling...

2008-01-15

2008-01-15

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C714S047300, C714S728000

Reexamination Certificate

active

07320114

ABSTRACT:
A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in the virtual IC and a software exception. A record of a type and a location of the soft error at the time of the injecting is created. The error log generated by hardware error correction is then compared with the record of injected error, the hardware error correction being part of the virtual IC. An IC design flaw is indicated when a discrepancy exists between the error log and the record of the injected error.

REFERENCES:
patent: 5944842 (1999-08-01), Propp et al.
patent: 6983414 (2006-01-01), Duschatko et al.
patent: 2004/0034820 (2004-02-01), Soltis et al.
patent: 2005/0172196 (2005-08-01), Osecky et al.

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