Method and system for using emission microscopy in physical...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C324S754120, C324S754090, C324S756010, C324S758010, C702S108000

Reexamination Certificate

active

06941529

ABSTRACT:
A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.

REFERENCES:
patent: 5768446 (1998-06-01), Reasoner et al.
patent: 5995647 (1999-11-01), Hamada
patent: 6038018 (2000-03-01), Yamazaki et al.
patent: 6553546 (2003-04-01), Murakami
patent: 6586952 (2003-07-01), Nozoe et al.
patent: 2002/0130262 (2002-09-01), Nakasuji et al.

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