Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-11-15
2005-11-15
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S203000
Reexamination Certificate
active
06965536
ABSTRACT:
A DRAM includes a set of secondary sense amplifiers as well as primary sense amplifiers coupled to respective digit lines of a DRAM array. The secondary sense amplifiers are coupled to the digit lines of an array through isolation transistors so that the secondary sense amplifier can be selectively isolated from the digit lines of an array. The DRAM also includes a refresh controller that periodically refreshes the DRAM on a row-by-row basis, and a command decoder that causes the refresh to be aborted in the even a read or a write command is received by the DRAM during a refresh. The refresh is aborted by saving the data stored in the row being refreshed in the secondary sense amplifiers and then isolating the sense amplifiers from the array. The memory access is then implemented in a normal manner. Since the DRAM can be accessed without waiting for the completion of a refresh in progress, the DRAM can be used as a cache memory in a computer system.
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Dorsey & Whitney LLP
Le Vu A.
Micro)n Technology, Inc.
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