Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-07
2002-06-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C438S201000
Reexamination Certificate
active
06410956
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory cells and more particularly to a method and system for using a spacer to reduce implant damage and lateral diffusion in the memory cell.
BACKGROUND OF THE INVENTION
A conventional flash memory cell includes a gate stack, a source, a drain, and a channel disposed between the source and the drain. To form a conventional memory cell, a tunnel oxide is grown on a semiconductor substrate. Typically, the gate stack is then formed on the tunnel oxide. The gate stack is then exposed to an oxidizing agent at a high temperature to grow a layer of oxide on the gate stack. Once the growth of the oxide layer is completed, the source and drain are implanted. In conventional flash memories including logic devices, once processing of the memory cells is completed, the logic device at the periphery is typically formed. For logic devices including a spacer, formation of the logic devices includes providing the spacer. The spacer in a logic device acts to space apart features of the logic device from the gate of the logic device.
The oxide layer is grown on the gate stack of the conventional memory cell for several purposes. One purpose of the oxide layer is to provide a spacer which serves to spatially separate the effects of a subsequent processing step from the edge of the gate stack. For example, the spacer separates the source and drain implants from the gate stack. This spacer helps reduce implant induced damage in the semiconductor near the gate stack. Thus, leakage of charge carriers between the floating gate and the source or drain due to damage in the semiconductor is reduced. In addition, growth of the oxide layer rounds the corner of the floating gate. This reduces electric fields which would otherwise be highly concentrated at the corner.
Although oxidizing the gate stack provides the spacer and rounds the corner of the floating gate, the oxidation step also lifts the edges of the floating gate. As the oxide grows on the gate stack, the oxide on the surface of the silicon continues to grow. Some oxide grows under the edges of the floating gate, lifting the edges of the floating gate.
Gate edge lifting is undesirable for many reasons. For example, gate edge lifting adversely affects erase and placement of the source. In order to erase the conventional memory cell, charge carriers tunnel from the floating gate to the source. Tunneling of charge carriers depends in part on the thickness of tunnel oxide through which the charge carriers must tunnel. To increase tunneling and raise erase efficiency, the tunnel oxide between the source and drain should be thin. Because of gate edge lifting, the source is typically driven farther under the gate to reach a thinner portion of the tunnel oxide. Driving the source farther under the gate makes the channel smaller. As a result, short channel effects, which degrade the performance of the memory cell, increase.
Accordingly, what is needed is a system and method for providing a memory cell having reduced implant induced damage near the source or drain and with reduced gate edge lifting. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for providing a memory cell on a semiconductor. In one aspect, the method and system comprise providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant. The gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system comprise providing at least one gate stack on a semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system comprise providing at least one gate stack on a semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.
According to the system and method disclosed herein, the present invention provides a memory cell having reduced short channel effects, thereby increasing overall system performance.
REFERENCES:
patent: 5470773 (1995-11-01), Liu et al.
Chan Vei-Han
Haddad Sameer
Luning Scott D.
Randolph Mark
Sobek Daniel
Advanced Micro Devices , Inc.
Huynh Andy
Nelms David
Sawyer Law Group LLP
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