Electronic digital logic circuitry – Reliability – Redundant
Reexamination Certificate
2001-12-10
2003-04-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Reliability
Redundant
C326S009000, C326S041000, C326S037000
Reexamination Certificate
active
06545501
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an application specific integrated circuit (ASIC) and more particularly to the use of a field programmable function within an ASIC.
BACKGROUND OF THE INVENTION
In today's business climate, internet technology (IT) customers increasingly require that common business applications utilizing IT equipment must meet mission-critical, 7 days a week, 24 hours a day requirements. Companies that transact business over the Internet, such as direct sales, have become world wide companies literally overnight. Companies such as these must be able to run their web access and server equipment 24 hours a day to meet world wide demand for their products and services.
Because of its low cost, commodity personal computer hardware and software has enabled IT administrators to utilize redundant systems and quick replacement parts to make up for inherently low system reliability. Now, however, parts reuse and parts recycling are becoming important issues as industry profit margins decrease and operating costs and environmental issues have become top priority items. Suppliers and customers will give priority to a process whereby failing hardware can be repaired and reused as long as the repair costs are minimal.
The reliability of a hardware subsystem is also improved by minimizing the intrinsic failure rate (IFR) of the components and/or by removing single points of failure. The IFR for a component can be improved through design refinement and/or manufacturing process refinement. Usually a “best IFR” limit is reached at which point it becomes cost prohibitive or physically impossible to reduce the IFR any further.
Redundant logic circuits and redundant components are a widely used method for achieving system reliability well beyond that which can be achieved through IFR efforts alone. Redundant circuits may also be used in the final stages of the ASIC manufacturing process to increase the percentage yield of shippable parts.
A common logic design method for standard cell parts uses redundant logic circuits which can be wired in during the ASIC manufacturing process to replace a failing logic circuit. A second design approach is to design an external interface to the ASIC connected to internal select logic to allow failed logic circuits to be swapped with redundant logic circuits in the field. Both of these design approaches require that every logic circuit be duplicated inside the ASIC and adds gate delays to the design, because they use select/deselect logic which invariably adds multiplexer logic delay.
Accordingly, what is needed is a system and method for field repair of a standard cell ASIC that overcomes the above-identified problems
SUMMARY OF THE INVENTION
An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell. The standard cell includes a plurality of logic functions. The ASIC further includes a field programmable (FP) logic function for coupling the plurality of logic functions together via a plurality of input and output stages. The FP logic function can be programmed for field repair of at least one of the plurality of the logic functions.
A method and system in accordance with the present invention utilizes a distributed field programmable logic block in conjunction with standard cells to provide for field repair and improved redundancy. To describe the features of the present invention in more detail, refer now to the following description in conjunction with the accompanying drawings.
REFERENCES:
patent: 6075381 (2000-06-01), LaBerge
patent: 6134173 (2000-10-01), Cliff et al.
patent: 6173419 (2001-01-01), Barnett
patent: 6178541 (2001-01-01), Joly et al.
patent: 6182206 (2001-01-01), Baxter
patent: 6182247 (2001-01-01), Hermann et al.
patent: 6191614 (2001-02-01), Schultz et al.
patent: 6209118 (2001-03-01), LaBerge
patent: 6181159 (2001-04-01), Rangasayee
patent: 6211697 (2001-04-01), Lien et al.
patent: 6219819 (2001-04-01), Vashi et al.
patent: 6219833 (2001-04-01), Solomon et al.
patent: 6223148 (2001-04-01), Stewart et al.
patent: 6223313 (2001-04-01), How et al.
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6230119 (2001-05-01), Mitchell
patent: 6237021 (2001-05-01), Drummond
patent: 6247147 (2001-06-01), Beenstra et al.
patent: 6249143 (2001-06-01), Zaveri et al.
patent: 6252422 (2001-06-01), Patel et al.
patent: 6253267 (2001-06-01), Kim et al.
patent: 6255845 (2001-07-01), Wong et al.
patent: 6256296 (2001-07-01), Ruziak et al.
patent: 6260087 (2001-07-01), Chang
patent: 6260182 (2001-07-01), Mohan et al.
patent: 6260185 (2001-07-01), Sasaki et al.
C. E.Kuhlmann et al., U.S. Pending Patent Application Ser. No. 10/016346 (docket RPS920010125US1), “Field Programmable Network Processor and Method for Customizing a Network Processor”/ No date.
R. T. Bailis et al., U.S. Pending Patent Application Ser. No. 10/016772 (docket RPS920010126US1), “Method and System for Use of an Embedded Field Programmable Gate Array Interconnect for Flexible I/O Connectivity”/ No date.
R. T. Bailis et al., U.S. Pending Patent Application Ser. No. 10/016449 (docket RPS920010127US1), “Method and System for Use of a Field Programmable Gate Array Function within an Application Specific Integrated Circuit (ASIC) to Enable Creation of a Debugger Client within the ASIC”/ No date.
R. T. Bailis et al., U.S. Pending Patent Application Ser. No 10/016448 (docket RPS920010128US1), “Method and System for Use of a Field Programmable Function within an Application Specific Integrated Circuit (ASIC) to Access Internal Signals for External Observation and Control”/ No date.
R. T. Bailis et al., U.S. Pending Patent Application Ser. No. 10/015922 (docket RPS920010129US1), “Method and System for Use of a Field Programmable Interconnect within an ASIC”/ No date.
R. T. Bailis et al., U.S. Pending Patent Application Ser. No. 10/015920 (docket RPS920010130US1), “Method and System for USe of a Field Programmable Function within a Chip to Enable Configurable I/O Signal Timing Characteristics”/ No date.
R. T. Bailis et al., U.S. Pending Patent Application Ser. No. 10/015921 (docket RPS920010132US1), “Method and System for Use of a Field Programmable Gate Array (FPGA) Cell for Controlling Access to On-Chip Functions of a System on a Chip (SOC) Integrated Circuit”/ No date.
Bailis Robert Thomas
Kuhlmann Charles Edward
Lingafelt Charles Steven
Rincon Ann Marie
International Business Machines - Corporation
Sawyer Law Group
Tokar Michael
Tran Anh Q
LandOfFree
Method and system for use of a field programmable function... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for use of a field programmable function..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for use of a field programmable function... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3011430