Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-07-10
2009-12-15
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C708S233000
Reexamination Certificate
active
07634631
ABSTRACT:
A method for updating a current network flow statistic stored in a memory device, comprising: storing a first statistic and a first address corresponding to a location in the memory device in a first stage of a multiple stage delay pipeline; shifting the first statistic and the first address to successive stages of the pipeline during successive clock cycles; at a middle stage of the pipeline, sending a read signal to the memory device to read the current statistic from the location; at a last stage of the pipeline, receiving the current statistic from the memory device in response to the read signal, adding the first statistic to the current statistic to generate an updated statistic, and sending a write signal to the memory device to write the updated statistic to the location; and, if a second statistic for the first address is stored in the first stage of the pipeline while the first statistic is stored in any but the first and last stages of the pipeline, replacing the first statistic with a sum of the first and second statistics and not sending the read signal when the second statistic is shifted to the middle stage.
REFERENCES:
patent: 6335992 (2002-01-01), Bala et al.
patent: 7017021 (2006-03-01), Gupta et al.
Alcatel Lucent
Bragdon Reginald G
Kramer & Amado P.C.
Vo Thanh D
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