Method and system for unfolding/replicating logic paths to...

Details Method and system for unfolding/replicating logic paths to... Method and system for unfolding/replicating logic paths to...

2006-05-19

2008-11-04

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07448015

ABSTRACT:
A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along the coincident portions to form non-intersecting, separate paths from the receive latch to two or more sinks. Common data or control inputs are provided for the gates in the replicated combinational logic. Driver logic may additionally be inserted along each replicated path, upstream of the combinational logic, to independently drive each of the sinks.

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