Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-05
2001-04-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C326S113000
Reexamination Certificate
active
06219822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuit design tools and, more particularly, to a system and method for tuning components for integrated circuits.
2. Description of the Related Art
The design of integrated circuits, for example very large scale integration (VLSI) circuits may be very time consuming and labor intensive. Many iterations are performed before a chip design is completed. The iterations required of chip designers often includes the following procedure:
1. Choose the logic and topology of the circuit to be designed.
2. Choose the initial sizes of the transistors and/or components to attempt to obtain the desired target performance of the circuit to be designed. This selection process typically involves an extensive visual inspection of the circuit and many hand calculations by the designer.
3. Run timing verification using computer aided design tools on the circuit to verify that the circuit has met its target performance.
4. If the desired target performance is not met, adjust the component, for example a transistor, sizes based on the timing results and repeat step 3. The adjustment of the component sizes in this step also includes an extensive visual inspection of the circuit and many calculations that are often performed by hand.
5. If it is not possible to meet the desired target performance using steps 3-4, alter the circuit topology and repeat steps 2-4. In addition, the designer needs to be able to obtain early estimates of circuit performance such that decisions can be made as early as possible as to whether a change in the circuit topology is essential to improve performance.
Steps 2 through 4 may be referred to as tuning steps for “tuning” the circuit. The conventional method as described above tends to be very time consuming and labor intensive. The conventional method usually relies on calculating an RC network in order to evaluate the circuit since this technique lends itself more readily to hand calculations. Therefore, a need exists for an improved system and method for tuning an integrated circuit which provides early estimates of maximum performance and rapid selection of component sizes that meets or exceeds desired performance. A further need exists for providing a more user friendly design tool for tuning integrated circuit designs.
SUMMARY OF THE INVENTION
A method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide tuning adjustment for sizes of the objects, assigning boolean expressions to represent timing or logical constraints on selected objects, evaluating the equations and the expressions to simulate the circuit in operation and adjusting the objects in the circuit until user defined criteria are achieved for the circuit.
In other methods of the present invention, the step of evaluating the equations and the expressions to simulate the circuit may include the step of measuring spacing between transitions on signals transmitted within the circuit to provide adjustments to the sizes of the objects in the circuit according to the spacings. The step of evaluating may include the step of evaluating slew according to the expressions. The step of evaluating may include the step of evaluating signal delay or any combination of evaluating slews and delays between objects according to the equations. The step of assigning Boolean expressions may include the step of representing the Boolean expressions by a simulated pulse, the simulated pulse compensating for signal spreading. The circuit may include both analog and digital objects. The objects may include transistors and parameterized subcircuits (p-cells). The step of automatically updating a schematic diagram for the circuit according to the adjusted sizes of the objects may also be included.
Another method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects, extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations and adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit.
In alternate methods of the present invention, the step of inputting equations may include the step of measuring spacing between transitions on the signals transmitted within the circuit to provide adjustments to the sizes of the objects in the circuit according to the spacings. The step of evaluating may include the step of evaluating slew according to the expressions. The step of inputting equations may include the step of evaluating signal delay between objects according to the equations. The step of extracting transition times may include the step of providing a simulated pulse between objects to represent Boolean expressions, the simulated pulse compensating for signal spreading. The circuit may include both analog and digital objects. The objects may include transistors and parameterized subcircuits. The step of automatically updating a schematic diagram for the circuit according to the adjusted sizes of the objects is preferably included.
A system for automatically tuning sizes of objects in an integrated circuit includes means for inputting equations associated with the objects to provide tuning adjustment for sizes of the objects. Means for assigning boolean expressions to represent timing constraints on selected objects is included. Computing means for evaluating the equations and the expressions to simulate the circuit in operation until user defined criteria are achieved for the circuit is also included.
In alternate embodiments, the timing constraints may include spacings between transitions on signals transmitted within the circuit, the spacings being utilized to provide adjustments to the sizes of the objects in the circuit. The timing constraints may include spacing differences between pulse widths of transmitted signals between the objects. The timing constraints may include spacing differences between predetermined transition points on transmitted signals between the objects. The timing constraints may include delay and slew between the objects. The circuit may include both analog and digital objects. The objects may include transistors and parameterized subcircuits.
Another system for automatically tuning sizes of objects in an integrated circuit includes means for inputting equations, the equations being associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects. Also, means for extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations is included. Means for adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit is also included.
In alternate embodiments, the transition times may include spacings between transitions on signals transmitted within the circuit, the spacings being utilized to provide adjustments to the sizes of the objects in the circuit. The transition times may include spacing differences between pulse widths of transmitted signals between the objects. The transition times may include spacing differences between predetermined transition points on transmitted signals between the objects. The timing information may include delay and slew between the objects. The circuit may includes analog and digital objects. The objects may include transistors and parameterized subcircuits.
These and other objects, features and advantages of the present invention will become apparent from the f
Gristede George D.
Hwang Wei
Tretz Christophe Robert
Do Thuan
F. Chau & Associates LLP
International Business Machines - Corporation
Smith Matthew
LandOfFree
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