Electrical computers and digital data processing systems: input/ – Interrupt processing – Source or destination identifier
Reexamination Certificate
1999-04-29
2002-10-01
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Source or destination identifier
C710S260000
Reexamination Certificate
active
06460105
ABSTRACT:
FIELD OF THE INVENTION
The present invention concerns a computer system and method of communication of interrupts in the computer system.
BACKGROUND TO THE INVENTION
In many applications there are more devices which may need interrupt capability than the processor has dedicated interrupt connections. In this case the interrupt request lines of each device may be OR-ed together and connected to a single interrupt pin belonging to the processor. When any one or more of the devices asserts an interrupt the processor interrupt line is asserted. The processor has the task of polling each device in turn. It normally does this by testing the interrupt bit of a status register of each device controller. When the identity of the interrupting device is determined, the processor can then call a routine associated with that interrupt source. This method is appropriate for slower devices or when there are few interrupting devices attached to the system.
Another existing system is generally called a vectored interrupt system. In such a system a separate device sometimes called a programmable interrupt controller (PIC) is connected to all devices which are capable of raising an interrupt. The PIC can be programmed to prioritise any interrupts it receives with respect to each other and, in some cases, with respect to the current priority of the processor. It can also contain a table which contains the association of interrupt handler routines and the interrupt source. In such a system a CPU is directed towards the routine by the PIC.
Another known interrupt system is referred to as a multi-processor interrupt system. In this example, an external device can be configured to provide vectored interrupts to multiple processors. A particular interrupt is associated with a vector and a CPU to which the interrupt request should be sent.
In the first prior art example the interrupt response can be very slow due to the fact that the processor may have to access many device registers before finding out the identity of the interrupt source. This can be slow and does not provide a mechanism for dealing with multiple processors.
The second example cannot be applied to multiple processors and multiple devices.
The third example requires the implementation of an auxiliary bus to carry interrupt signals to multiple processors. This requires extra pins or signals and extra logic to implement whatever protocol applies to the use of these signals.
Interrupts generally occur as a result of a change in state of a peripheral device, caused by some activities of the peripheral device. This change in state is generally represented by an electrical condition, such as the voltage or current level on an output wire. In the prior art, the pins and signal lines carry these state changes to whatever is responsible for dealing with the interrupts. Thus, even in the situation where there is a centralised programmable interrupt controller, there must still be dedicated lines from each peripheral device carrying the state information directly to the central controller. It is one aim of the present invention to remove this requirement for dedicated interrupt lines.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided a method of transmitting an interrupt represented by an electrical level of a conductor from a peripheral device to a receiving module by:
detecting the electrical level of the conductor;
constructing a message packet to transmit the interrupt when it is detected that the electrical level has changed between a logical zero level and a logical one level;
transmitting the message packet from the peripheral device to the receiving module; and
at the receiving module, handling the message packet to act on the interrupt by implementing an interrupt handling routine.
According to another aspect, the invention also provides computer system comprising at least one peripheral device and a processor in communication with the peripheral device via a routing path, wherein the peripheral device is associated with circuitry for detecting the electrical level of a conductor representing an interrupt and a packet assembler for constructing a message packet when it is detected that the electrical level of the conductor has changed between a logical zero level and a logical one level, wherein the message packet is transmitted from the peripheral device to the processor via the routing path, and wherein the processor includes a packet handler for handling the message packet to act on the interrupt by implementing an interrupt handling routine.
In one embodiment of the invention interrupts are communicated between a number of different peripheral devices and processors in a computer system using discrete event packets. A device wanting to raise an interrupt fabricates an event packet which specifies the processor which is to service the interrupt, and an indication of the origin of the interrupt. This packet is routed to the specified processor. The receiving processor is able to call the interrupt handling routine corresponding to that interrupt either directly or indirectly through a table in a conventional manner. The event packets can carry indications of the interrupt being edge-triggered or level sensitive.
Unlike the prior art, no extra connectivity is required between peripheral devices and any of the processors which can service interrupts.
In one arrangement, the message packet includes identification of the peripheral device which generated the interrupt and the receiving module includes an interrupt handling routine dependent on that identity.
In another arrangement, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts and the receiving module generates a response packet including the same transaction identifier.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.
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British Search Report from Application No. 9809186.1, filed Apr. 29, 1998.
Betts Andrew Keith
Farrall Glenn Ashley
Foster Brian
Jones Andrew Michael
Sturges Andrew Craig
Lefkowitz Sumati
Morris James H.
Skrivanek, Jr. Robert A.
STMicroelectronics Limited
Wolf Greenfield & Sacks P.C.
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