Method and system for translation lookaside buffer coherence...

Details Method and system for translation lookaside buffer coherence... Method and system for translation lookaside buffer coherence...

2005-08-16

2005-08-16

Bragdon, Reginald G. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S141000, C711S144000, C711S133000

Reexamination Certificate

active

06931510

ABSTRACT:
This invention is an apparatus, method, and system for translational lookaside buffer coherency in computer systems having a plurality of processors, each having an associated TLB for storing address translation data, and the computer system having a plurality of independent paths upon which the plurality of processors are distributed and a TLB message transmitted on said plurality of independent paths.

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patent: 5946717 (1999-08-01), Uchibori
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patent: 6119204 (2000-09-01), Chang et al.
patent: 6263403 (2001-07-01), Traynor
patent: 0 592 121 (1994-04-01), None
Black, et al., “Translation Lookaside Buffer Consistency: A Software Approach”, Architectural Support for Progr. Lang. & Operat. Systems, Apr. 3, 1989, pp. 113-122.
IBM Technical Disclosure Bulletin, “Simplified Table Lookaside Buffer-Handling Mechanism for a Multi-Processor”, vol. 34, No. 12, May 1992, pp. 164-166.
PCT International Search Report for PCT/US 01/23792, date of mailing Jul. 16, 2002.

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