Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
1999-04-09
2001-05-22
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S090000
Reexamination Certificate
active
06236233
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer systems, and more particularly to disk drives in computer systems.
BACKGROUND OF THE INVENTION
Disk drives are well known components of computer systems. One type of disk drive which is commonly used in computer systems is a Direct Access Storage Device (DASD).
FIG. 1
is a block diagram illustrating a conventional system with a DASD. The system
100
comprises a host
102
which exchanges data via connection
104
with the DASD
106
. The DASD
106
comprises Drive Electronics
108
, Arm Electronics
110
(AE), and a Head and Disk Assembly
112
. The AE
110
is generically referred to by many in the art as a “pre-amp chip”.
FIG. 2
is a block diagram illustrating the AE
110
and the Head and Disk Assembly
112
in more detail. The Head and Disk Assembly
112
comprises a plurality of disks
114
for storing data, a Spindle Motor
116
which controls the speed at which each disk
114
spins, connections
117
between the AE
110
and the Head and Disk Assembly
112
, and heads
118
(
a
)-
118
(
f
). There is one pair of heads
118
(
a
)-
118
(
f
) for each disk
114
, one head for each surface of the disk. The heads
118
(
a
)-
118
(
f
) read data from and write data to their respective disks. The heads
118
(
a
)-
118
(
f
) are positioned over specific tracks on the disks
114
by a Head Positioning Motor
120
. Both the Head Positioning Motor
120
and the Spindle Motor
116
are controlled by signals to and from a Positioning Control Unit
150
. The AE
110
also communicates with the Drive Electronics
108
.
There is a continuing demand in the industry for the data transfer rate from the disks
114
to the Drive Electronics
108
to be faster. One way to accomplish this is to use a BiCMOS4S chip, developed by INTERNATIONAL BUSINESS MACHINES CORPORATION, as the AE
110
. The BiCMOS4S chip uses a silicon technology which allows for a fast data transfer rate. The BiCMOS4S silicon technology is well known in the art and will not be discussed in detail here.
However, the architecture of the BiCMOS4S chip negatively biases the substrate and imposes a voltage limit on its components. The chip is charged at a positive Vcc, for example of +5V, and a Vee below ground, for example of −4V. Vcc represents the voltage from a positive power supply; Vee represents the voltage from a negative power supply. The voltage limit on the chip components is Vcc−Vee. This creates a problem when a signal from the chip is to be driven off-chip to devices which use standard Transistor Transistor Logic (TTL) logic levels. Standard TTL-compatible devices are typically designed to function at a positive Vcc and ground. This problem is compounded by the fact that components used within the chip are also designed to function within a chip charged at a positive Vcc and ground.
Accordingly, there exists a need for a method and system for translating a signal from a chip with a negative substrate bias. The method and system should translate the signal such that it is compatible with standard TTL logic levels. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for translating a signal from a chip with a negative substrate bias. The method and system includes receiving an input signal in a first state in a first logic level, the first state being approximately at ground; and translating the input signal to a second state in a second logic level, the second state being above ground. The method and system translates a signal from a chip with a negative substrate bias. In the preferred embodiment, the method and system of the present invention uses a translation circuit to translate and drive the signal off-chip. The translation circuit in accordance with the present invention functions with a positive Vcc and a Vee lower than ground, and also does not violate any of the rules of functionality for components used in a chip which has a negatively biased substrate and a voltage limit on its components. The method and system allows the translated signal to be driven off-chip and be compatible with standard TTL logic levels. A pre-amp chip which uses the translation circuit of the present invention is able to maintain a fast data rate and to take advantage of the low cost of the silicon process used for the chip.
REFERENCES:
patent: 4677320 (1987-06-01), Hannington
patent: 4857776 (1989-08-01), Khan
patent: 4996452 (1991-02-01), Yee et al.
patent: 5120999 (1992-06-01), Schreck et al.
patent: 5138199 (1992-08-01), Hirata et al.
patent: 5434518 (1995-07-01), Sinh et al.
patent: 5561388 (1996-10-01), Kumagai
patent: 6051995 (2000-04-01), Pollachek
Bluestone Randall J.
Cho James A.
International Business Machines - Corporation
Sawyer Law Group LLP
Tokar Michael
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