Method and system for tiling a bias design to facilitate...

Details Method and system for tiling a bias design to facilitate... Method and system for tiling a bias design to facilitate...

2007-12-25

2007-12-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10964409

ABSTRACT:
A method and system for tiling a bias design for an integrated circuit device to facilitate efficient design rule checking. The method is implemented in a computer implemented design synthesis system. The method includes receiving a circuit netlist, wherein the circuit netlist represents an integrated circuit design to be realized in physical form. A deep N-well bias voltage distribution structure is provided within the circuit netlist, wherein the structure includes a plurality of tiles arranged to distribute a bias voltage to a plurality of N-wells of the circuit netlist.

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