Method and system for throttling data packets in a data...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol

Reexamination Certificate

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Details

C710S110000, C370S231000, C370S235000, C370S428000, C370S429000

Reexamination Certificate

active

11095420

ABSTRACT:
A system for controlling packet transfers includes a packet transfer core; an application layer coupled to the packet transfer core by an application interface; a buffer in the packet transfer core for receiving packets from a packet source and transferring the packets to the application layer over the application interface, the packets comprising one or more words; a register in the application layer for receiving packets from the application interface; and a client device for receiving packets transferred thereto from the register. When the client is unable to receive packets from the register, the client asserts a first wait signal to the register, causing the register to continue receiving packets from the interface and storing the packets without transferring the packets to the client. When the register is unable to continue receiving packets from the interface, the register asserts a second wait signal to the buffer over the application interface, causing the buffer to continue receiving packets from the packet source and storing the packets without transferring packets to the interface.

REFERENCES:
patent: 5287316 (1994-02-01), Urushidani et al.
patent: 6222840 (2001-04-01), Walker et al.
patent: 6657999 (2003-12-01), Brewer
patent: 6940863 (2005-09-01), Xue et al.
patent: 2005/0128299 (2005-06-01), Inokuma

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