Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-01
2010-02-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07665044
ABSTRACT:
A method and a system to pre-scan a file, analyze data and create the Condensed Macro Library (CML) file. The method used is to find macros or cells of certain classes that are defined by rules. After a suitable macro or cell is identified, a parser scans the macro or cell pins and finds pins which have ports with the shapes defined on the specific layers defined by the rules and user data. Further processing is then performed based on a set of rules and the pin data to generate a CML file that contains relevant information regarding relevant pins.
REFERENCES:
patent: 6907589 (2005-06-01), Frank et al.
patent: 7353476 (2008-04-01), Imada et al.
patent: 2006/0218516 (2006-09-01), McLain et al.
Cadence Design Systems, Inc. “What's New in LEF/DEF” Product Version 5.5, Dec. 2002, updated Apr. 2004, Cadence Design Systems, Inc., San Jose, CA.
Cadence Design Systems, Inc. “LEF/DEF 5.5 Language Reference” Product Version 5.5, Apr. 2004, Cadence Design Systems, Inc., San Jose, CA.
Carlson Brian J.
Khomoutov Alexander F.
Cadence Design Systems Inc.
Siek Vuthe
Vista IP Law Group LLP
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