Method and system for testing the compliance of PCIE...

Details Method and system for testing the compliance of PCIE... Method and system for testing the compliance of PCIE...

2011-06-14

2011-06-14

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S712000, C710S106000, C710S313000, C370S224000, C370S249000, C375S221000

Reexamination Certificate

active

07962808

ABSTRACT:
The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE expansion system comprises delivering the data signals from the data lanes to a compliance board that is configured to loop back at least a first portion of the data signals and transmit a complementary second portion of the data signals to a testing device, and testing a compliance of the second portion of the data signals with the PCIE requirements. The first portion of the data signals is then tested through a second compliance board that is configured to loop back the second portion of the data signals and transmit the first portion of the data signals to the testing device.

REFERENCES:
patent: 7132823 (2006-11-01), Ng et al.
patent: 7231560 (2007-06-01), Lai et al.
patent: 7434118 (2008-10-01), Moessinger et al.
patent: 7437643 (2008-10-01), Khanna et al.
patent: 7447953 (2008-11-01), Vogt
patent: 7464307 (2008-12-01), Nejedlo et al.
Keezer et al., Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses, Jan.-Feb. 2006, IEEE, pp. 46-57.

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