Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-10-08
2001-04-10
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06216241
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronic memories and more particularly to methods and systems for testing such memories.
DESCRIPTION OF THE RELATED ART
Multiport memories are increasingly being used for a variety of applications. They allow for simultaneous reading and writing to arbitrary addresses through separate read and write ports.
A multiport memory typically consists of a basic memory block surrounded by ancillary circuitry to provide for access and synchronization. This circuitry includes read and write address buffers and decoders, input data latches, output data buffers, normal or tristate, and a clock buffer. The data cells can be written to by latching the data into an input data latch, providing the address to be written to a write address buffer, then enabling writing. A finite specified time after the following clock edge, the addressed memory cell contains the desired data. Reading is achieved by latching the address of the data to be read into a read address buffer. After a finite amount of time, the addressed data appears on the output of the output buffers.
The presence of separate read and write ports permits concurrent reading and writing of different memory cells. If the same cell is written and read at the same time, the result of the read is undefined. The use of 2×1 multiplexers controlled by the least significant bit (LSB) of the address line in the memory block allows for two columns of cells to share one write word line.
SUMMARY OF THE INVENTION
The inventors have found that a problem can arise, if a cell is written or read using one port while an adjacent cell is being read or written, respectively, using another port. Assuming manufacturing or operational variations, the adjacent write and read lines both at the high voltage level, can produce enough current flow to cause the inverter used to store the memory bits to change a correct value to an incorrect value, or cause an incorrect value to be stored.
Thus, the inventors have discovered a type of memory fault which may cause an error when a first memory cell is written to, at the same time that a neighboring cell (having an address that is the same as that of the first cell, except for inversion of the least significant bit) is being read. Allowing both read and write ports to access neighboring memory cells simultaneously gives rise to the possibility of interference of operations on neighbor cells causing an incorrect value to be stored, or a correct value to be changed. Thus, it is desirable to implement tests which are intended to detect these failures, as well as the more traditional ones.
The present invention is a method for testing a memory device to detect a memory fault of the type described above, which causes an error to occur when a first memory cell is written to, at the same time that a neighboring cell is being read. The combination of operations which cause the error is referred to herein as, “write-disturb,” and is designated by the notation, W∥D.
A memory device has first and second neighboring memory cells. The second cell is written to have a predetermined value. A first datum is in the first memory cell. The datum in the second memory cell is read at the same time that the first memory cell is being written to. If the datum read does not match a predetermined second datum, then an error is detected. The datum in the second memory cell is read again, after the W∥D step. Another comparison is made to determine whether the data read after the W∥D step match the predetermined second datum. A fault is detected in the memory device, if the data read do not match the second datum.
Further, a method according to the invention may include additional steps for detecting other types of memory faults known in the art, such as “stuck at 0/1” faults, transition faults, single static coupling faults, single dynamic coupling faults, multi-port faults, read/write logic faults, and address decoder faults.
The invention may also be embodied in apparatus for performing the test method. The apparatus may be included in a memory tester or a built-in self test circuit for a memory device. The invention may also be embodied in a computer readable medium storing computer program code for causing a computer or memory tester to perform the test method.
REFERENCES:
patent: 5436911 (1995-07-01), Mori
patent: 5675544 (1997-10-01), Hashimoto
“Testing Semiconductor Memories Theory and Practice”, By A.J. van de Goor, John Wiley & Sons, Ltd., West Sussex, England, 1996 pp. 63 and 65-92.
Advertisement from Internet entitled “Aries Platform High Speed Memory Test Systems” by Teradyne, Inc., Boston, MA; (1996) pp. 1-3.
Abstract entitled “Simple and Efficient Algorithms for Functional Ram Testing” by Marian Marinescu from the 1982 IEEE Test Conference, pp. 236-239.
Fenstermaker Larry Ray
Higgins Frank P.
Kim Ilyoung
Lewandowski James Louis
Nagy Jeffrey Jay
Agere Systems Guardian Corp.
Chung Phung M.
Duane Morris & Heckscher LLP
Koffs Steven E.
LandOfFree
Method and system for testing multiport memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for testing multiport memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for testing multiport memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2458416