Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2000-07-14
2003-06-17
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C713S400000, C714S003000, C714S044000, C714S048000, C714S701000, C714S775000, C714S781000
Reexamination Certificate
active
06581114
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to communication systems and components and specifically to a method and system for synchronizing serial data.
BACKGROUND OF THE INVENTION
The present invention deals with communication systems. Serial communication utilizes a single communication path to transmit data from a first point to a second point. When multi-bit words are communicated, they can be transmitted one after the other along the serial line. It is then up to the receiver to discern which bits belong to each word. This sorting process can be referred to as resynchronization.
FIG. 1
shows part of the resynchronization logic in a prior art serial communications system. The resynchronization logic shown in
FIG. 1
will be present in each of two units communicating with one another. The transmitted data
114
of one such unit will be the same as the received data
116
of the other unit. The received data is provided to 8b10b decoder
120
. As known in the art, an 8b10b code is a code that translates an 8-bit data word into a 10-bit word for communications. For data, this block converts the 10 bits of received data into the originally transmitted 8 bits and outputs this as decoded data. Decoder
120
also asserts the Data Valid signal when valid data is found.
Decoder
120
provides a Data Error signal to idle code generator
122
. The Data Error signal is asserted when an unrecognized word is received by decoder
120
. Upon this occurrence, idle code generator
122
will instruct 8b10b encoder
126
to transmit an idle code. The encoder
126
will also send an idle code at predetermined times determined by the system protocol. This transmission is initiated by system protocol generator
124
, which sends an indication to send an idle code to idle code generator
122
.
In order to support this recovery method, the transmitter effectively echoes the data-error status from the receiver, sending either a valid data code—group back to the receiver side or sending a valid special code-group back to the receiver side. In the receiver, these received code-groups are characterized and a data-valid signal is developed that represents whether the code-groups from the transmitter are data or special codes. One aspect of the prior art that is utilized by the preferred embodiment of the present invention is that the system protocol generator
124
sends idle codes or user data in packet size chunks, not anything smaller.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention utilizes this feature of the prior art to search for idle codes or data that has been transmitted in a chunk that is less than a full packet size. If such a transmission is found, the system can determine that an error exists and act appropriately to correct this error. For example, it may be likely that the serial data is not properly synchronized and the system must act to correct this problem.
As a first example,
FIG. 3
illustrates a first embodiment system
312
of the present invention. In the prior art system of
FIG. 1
, out-of-sync data will frequently be interpreted as an invalid code-group by the 8b10b decoder
120
in the receiver, generating a data-error signal, which fluctuates almost randomly at the data word rate.
As a first example,
FIG. 3
illustrates a first embodiment system
312
of the present invention. In the prior art system of
FIG. 1
, out-of-sync data will frequently be interpreted as an invalid code-group by the 8b10b decoder
120
in the receiver, generating a data-error signal, which fluctuates almost randomly at the data word rate.
Similar to
FIG. 1
, the first embodiment
312
of the present invention will be present in each of two units communicating with one another. The transmitted data
316
of one such unit will be the same as the received data
314
of the other unit. The first embodiment
312
utilizes an out-of-sync detector circuit
330
that monitors the data-valid line from the receiver.
FIG. 3
shows a block diagram of this embodiment of the invention. Elements
320
,
322
,
324
and
326
can be similar to the analogous elements
120
,
122
,
124
and
126
described with respect to FIG.
1
. Therefore, any description of those elements would also apply to the
FIG. 3
description.
Different aspects of the present invention provide a number of advantages over other possible techniques. For example, with the preferred embodiment of the present invention is not necessary to send comma codes frequently, or even at all. Further, it is not necessary to embed check words into the user data sequence to determine if it was suffering errors. Although there is nothing in the present invention that precludes these additional checks, serial link bandwidth can be saved by limiting the additional bits. Since serial link bandwidth is not used during normal operation to monitor the link integrity, more link bandwidth is available for the system performance.
Further, the preferred embodiment implementation does not require disturbing existing packet protocols or data formats, and it does not require sending extra codes to monitor the data integrity of the serial link. This preferred method essentially recognizes the increased signaling bandwidth used by the system when it goes out-of-sync. In the vast majority of cases, existing packet protocols are not disturbed by utilizing this invention. This permits modular design practice where the packetization can be developed independently of the lower level link maintenance functions of the design. The preferred embodiment of the invention simply expects normal system operation to have a minimum packet size greater than one data word, a very easy constraint to meet.
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King Justin
Moore J. Dennis
Ray Gopal C.
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