Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural oscillators controlled
Reexamination Certificate
1999-11-29
2001-02-13
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural oscillators controlled
C331S00100A, C331S173000, C327S142000, C327S147000, C327S151000, C327S153000, C327S295000, C327S297000
Reexamination Certificate
active
06188286
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to clock synchronization, and more specifically to clock synchronization using one voltage-controlled oscillator for synchronizing multiple chips or subsystems.
BACKGROUND OF THE INVENTION
As the operating frequency of complex digital communication and data transfer systems increase, there is major challenge to operate the entire digital system in a synchronous manner. Typically, a complex digital system includes various chips each having circuitry associated with one subsystem that needs to exchange information with other subsystems. The exchange of information between the various subsystems must be synchronized in order to prevent loss or corruption of the exchanged information.
For example, if the complex digital system operates in an Asynchronous Transfer Mode (ATM) network, each subsystem may be responsible for extracting a data signal from one of several cells. The data signal may represent voice, video or any other type of synchronous signal. Briefly, ATM is a standard that describes the process for packetizing a synchronous signal into a cell so that voice, video, data or other information may be sent over the same network. Each cell has a fixed size and includes a header and a payload. The synchronous signal information is placed in the payload of a cell and the cell is interleaved with cells from other sources. These cells are then delivered to a destination. At the destination, individual cells are extracted to reconstruct the original synchronous signals.
As mentioned earlier, typically, one subsystem is responsible for reconstructing one of the original synchronous signals from the packetized cells. Therefore, each subsystem must be synchronized with the other subsystems so that the data from the various signals is not corrupted as a result of clock skew between the subsystems. The problem with clock skew (i.e. phase difference) between the reference clocks for the various subsystems becomes even greater as the internal operating frequencies increase above several hundred megahertz (MHz). Therefore, with the increasing desire for greater internal operating frequencies, a synchronization scheme with a high degree of synchronization among the subsystems becomes increasingly important.
One prior art synchronization scheme has a phase alignment circuit for each subsystem.
FIG. 1
is a functional block diagram of a prior art phase alignment circuit
10
. The phase alignment circuit
10
includes a phase detector
12
, a loop filter
14
and a voltage-controlled oscillator (VCO). The loop filter
14
is connected to an output signal V_VCO of the phase detector
12
and a control input of the VCO. The phase detector
12
has two inputs: a reference signal C_SYS and an output signal connected directly or indirectly from the VCO. As one skilled in the art will appreciate, the VCO may generate the output signal C_VCO to be any frequency that is a multiple of the C_SYS signal. For example, the C_SYS signal may be at 8 MHz and the VCO may generate the signal C_VCO at 32 MHz. The higher frequency C_VCO signal is then used internally as a clock for the subsystem. If the C_VCO signal is at a higher frequency then the reference signal C_SYS, the C_VCO signal is input to a divider
16
to produce a signal C_SYS_INT having the same frequency as reference signal C_SYS. The output of the divider
16
is then directly connected to the phase detector
12
instead of having the signal C_VCO directly connected from the VCO. For the remaining of the disclosure, the signal C_SYS_INT will be used to refer to the input to the phase detector
12
.
In operation, the phase detector
12
compares the phase of the reference signal C_SYS against the phase of the signal C_SYS_INT produced by the VCO. The difference voltage signal V_VCO generated by the phase detector
12
is a measure of the phase difference between the two input signals, C_SYS and C_SYS_INT. The difference voltage signal V_VCO is filtered by the loop filter
14
to produce a control voltage which is then applied to the VCO. Application of the control voltage to the VCO changes the frequency of the output signal C_VCO produced by the VCO in a direction that reduces the phase difference between the input signal C_SYS_INT and the reference signal C_SYS.
FIG. 2
is a timing diagram of the phase alignment or convergence of C_SYS_INT with C_SYS in the phase alignment circuit
10
shown in
FIG. 1
at three different lock-in phase states: 0 degree phase difference; 90 degree phase difference; and 180 degree phase difference. In general, one skilled in the art will appreciate that for each starting state, as the average voltage increases, the loop filter
14
produces a control voltage that causes the VCO to change the frequency F_CVO of the output signal C_VCO to reduce the phase difference between the two input signals of the phase detector
12
. Once the signals are phase aligned, the signals are then in one of the lock-in states illustrated in FIG.
2
.
Typically, as mentioned earlier, a complex digital system may have several subsystems that need to be phase aligned with the reference signal C_SYS. Therefore, in this prior art system, each subsystem has a dedicated VCO and a phase alignment circuit
10
to synchronize the C_SYS_INT signal in each subsystem. Having a VCO and a phase detection mechanism for each subsystem requires a large amount of board space and increases the costs associated with the digital system. In addition, the quality of the reconstructed synchronous signals in the digital system may be lower due to the interference and noise caused by multiple voltage-controlled oscillators (VCOs) operating in close proximity.
Accordingly, there is a present need in the art for a synchronization scheme for multiple chip configurations that minimizes board space and provides a stable synchronized signal for reconstructing signals with high quality.
SUMMARY OF THE INVENTION
The present invention overcomes the limitations identified above by providing a method and system for synchronizing multiple chips or subsystems using only one voltage-controlled oscillator. An external system clock is applied to one of the subsystems that is designated as a master. The master includes a voltage-controlled oscillator (VCO) that produces a VCO clocking signal having a frequency that is a multiple of the external system clock and is phase aligned therewith. An internal clock signal is produced within the master having a frequency equal to the external system clock and is phase aligned with the VCO clocking signal. The master generates a synchronization signal that marks a predefined edge of the internal clock signal.
To synchronize all the subsystems, the VCO clocking signal is supplied to each subsystem so that it arrives with the same phase. In addition, the synchronization signal is supplied to each subsystem which samples the synchronization signal with an edge of the VCO clocking signal to determine when the predefined edge of the internal clock signal of the master has occurred. Because the internal clock signal has a frequency that is a known fraction of the VCO clocking signal, the subsystem delays for a predefined number of period of the VCO clocking signal before realigning its own internal clocking signal. As a result, the internal clock signal of the salve subsystem is synchronized with the internal clock of the master.
Because the first internal clock and the second internal clock are synchronized, all the subsystems clock incoming data at an identical time. Therefore, the present invention achieves synchronized operation between multiple subsystems using only one voltage-controlled oscillator. Consequently, the present invention reduces the cost and the board space for any digital system in comparison with the synchronization schemes in the prior art.
REFERENCES:
patent: 4282493 (1981-08-01), Moreau
patent: 4868513 (1989-09-01), Piercy et al.
patent: 5056118 (1991-10-01), Sun
patent: 5142246 (1992-08-01), Petersson
patent: 5148334 (1992-09-01), Takeuchi et al.
pat
Fiedler Ulrich
Hogl Erik
Infineon Technologies North America Corp.
Mis David
LandOfFree
Method and system for synchronizing multiple subsystems... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for synchronizing multiple subsystems..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for synchronizing multiple subsystems... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2612575