Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2000-03-20

2001-11-13

Nguyen, Matthew (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C257S357000

Reexamination Certificate

active

06317306

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89104357, filed Mar. 10, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an ESD protection circuit, of which the parasitic BJT can be turned on in advance by triggering a substrate under ESD stress conditions, so that the ESD capacity can be enhanced.
2. Description of the Related Art
Electrostatic discharge (ESD) can easily damage IC devices such as DRAMs and SRAMs during both manufacture and operation. A person walking on a carpet, for instance, can carry up to several thousand volts of electrostatic charge under high relative humidity (RH) conditions and over 10,000 volts under low RH conditions. If such a person touches an IC package, the electrostatic charge on his/her body is instantly discharged to the IC package, thus causing ESD damage to the internal circuitry of the IC package. A widely used solution to this problem is to provide an on-chip ESD protection circuit around each I/O pad of the IC package.
One drawback to the prior art, however, is that when the IC device is fabricated by scaled down technology, such as the deep-submicron CMOS process, the gate-oxide structure is reduced in thickness. This causes the breakdown voltage of the gate-oxide structure to be close to or below the breakdown voltage at the source/drain junction, thus degrading the ESD protection capability. The internal circuitry of an IC device is typically drawn in accordance with the Minimum Design Rules. Therefore, the various semiconductor components of an IC device are designed to have the minimum size. This practice, however, makes some components vulnerable to ESD stress when these components are further scaled down. For this reason, a highly integrated IC device fabricated by deep-submicron process is particularly vulnerable to ESD. Therefore, in the IC industry, much research effort has been directed to ESD protection for integrated circuitry.
FIG. 1
is a circuit diagram for a conventional ESD protection circuit. As shown in
FIG. 1
, in order to protect the internal circuit
16
, the ESD current imported through an input/output (I/O) pad
10
can be discharged not only through an NMOS transistor
12
to the ground VSS but also through a PMOS transistor
14
to a voltage source VDD.
The conventional ESD protection circuits as described above and shown in
FIG. 1
utilizes junction breakdown voltage to protect the internal circuit
16
from damage. In order to protect internal circuit
16
, the conventional operation method utilizes a parasitic bipolar device to discharge the ESD current imported through the I/O pad
10
, that is, the conventional method utilizes hole current (electron current) generated by drain junction avalanche breakdown to trigger a P-N junction (that is, trigger a parasitic BJT to turn on) between substrate and source of NMOS transistor
12
(or PMOS transistor
14
) to turn on.
However, whether the P-N junction between substrate and source is easily turned on has a direct effect on the ESD protection circuit capability. Thus, in the future development for ESD protection circuit, this is a key technology for how to advanced turn on parasitic BJT in ESD stress condition so as to enhance the internal circuit protection capability.
In addition, when the IC device is fabricated by a scaled down CMOS process and the gate-oxide structure is accordingly reduced in thickness, some problems arise; for example, the breakdown voltage of the gate-oxide structure happens earlier than the junction breakdown voltage at the source/drain junction. In other words, if the breakdown voltage of the gate-oxide structure happens earlier than the junction breakdown voltage at the source/drain junction, then the conventional ESD protection circuits shown in
FIG. 1
lose their protective ability.
SUMMARY OF THE INVENTION
The invention provides an electrostatic discharge (ESD) protection circuit disposed between an I/O pad and an internal circuit. The ESD protection circuit comprises two NMOS transistors and two PMOS transistors. A first NMOS transistor further comprises a source terminal, a drain terminal, a gate terminal and a substrate terminal, wherein the source and gate terminals are connected to a ground voltage and the drain terminal is connected to the I/O pad. A second NMOS transistor further comprises a source terminal, a drain terminal, a gate terminal and a substrate terminal, wherein the source terminal is connected to the I/O pad, the drain terminal is connected to a voltage source and the gate and substrate terminals are connected to the ground voltage. A first PMOS transistor further comprises a source terminal, a drain terminal, a gate terminal and a substrate terminal, wherein the drain terminal is connected to the ground voltage and the substrate terminal of the first NMOS transistor, the gate terminal is connected to the voltage source and the source and substrate terminals are connected to the I/O pad. Finally, a second PMOS transistor further comprises a source terminal, a drain terminal, a gate terminal and a substrate terminal, wherein the source and gate terminals are connected to the voltage source, the drain terminal is connected to the I/O pad and the substrate terminal is connected to the drain terminal of the second NMOS transistor. Furthermore, the ESD protection circuit of the invention further comprises a first resistor and a second resistor, wherein the first resistor is disposed between the drain terminal of the first PMOS transistor and the ground voltage, and the second resistor is disposed between the drain terminal of the second NMOS transistor and the voltage source.
According to the ESD protection circuit of the invention, whether a positive voltage stress is applied to ground voltage VSS or a negative voltage stress is applied to voltage source VDD, both the parasitic BJT of the first NMOS transistor and the second PMOS transistor can be turned on in advance by triggering the junctions between their substrates and sources, and the ESD stress then can be discharged to the ground voltage VSS and the voltage source VDD, so that the capacity of the ESD protection circuit in this invention is thus improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5208719 (1993-05-01), Wei
patent: 6128171 (2000-10-01), Iniewski et al.
patent: 6160457 (2000-12-01), Wu

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