Method and system for synchronizing a clock frequency...

Details Method and system for synchronizing a clock frequency... Method and system for synchronizing a clock frequency...

2005-08-09

2005-08-09

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S002000, C713S100000

Reexamination Certificate

active

06928540

ABSTRACT:
A system and a method capable of automatically reading out the multiple value of clock frequency on system bus are provided. The system includes a central processing unit and a chipset. The central processing unit has a storage unit for holding a multiple value of clock frequency. The storage unit is capable of synchronizing with an external device through a serial initialization packet (SIP) protocol. The chipset attempts to synchronize with the central processing unit in a SIP protocol that uses a preset multiple value of clock frequency as a parameter. If synchronization between the central processing unit and the chipset cannot be established, the preset multiple value of clock frequency is changed and the SIP protocol is executed again. The multiple value of clock frequency is reset until synchronization is established. After synchronization, the multiple value of clock frequency in the central processing unit is retrieved and compared with the preset multiple value of clock frequency. If the retrieved multiple value of clock frequency is different from the preset value in the chipset, the preset value is replaced by the retrieved value.

REFERENCES:
patent: 5862351 (1999-01-01), He
patent: 6269443 (2001-07-01), Poisner et al.
“AMD Duron Processor Data Sheet”, Sep. 2000, pp. 33-35.

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