Electronic digital logic circuitry – Multifunctional or programmable – Field-effect transistor
Reexamination Certificate
1997-12-18
2002-01-22
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Field-effect transistor
C326S056000, C326S082000
Reexamination Certificate
active
06340898
ABSTRACT:
1. Field of the Invention
The present invention relates to data networks, and more particularly, to a control system that allows a totem-pole output driver to be configured as an open-drain output driver.
2. Background Art
The growth in computer applications that require heavy data traffic and the increasing availability of high-speed transmission lines and intelligent communication switches create a need for computer systems able to manage a huge amount of data at high rates. For example, high-speed communication networks may require a central processing unit (CPU) to be interrupted at rates of 20,000-100,000 interrupts per second in response to hundreds various events.
In a network controller chip, interrupt signals to an external CPU are sent via an output driver connected to an interrupt pin of the chip. In some applications, a totem-pole driver is used as the output driver, whereas in other applications an open-drain driver is employed.
As shown in
FIG. 1
, an exemplary totem-pole output driver
10
for driving an output of a chip may comprise a pair of P-type and N-type MOS transistors P
1
and N
1
connected between a voltage source Vcc and a ground terminal. The transistor P
1
may act as a pull-up transistor, and the transistor N
1
may be a pull-down transistor. A data signal from internal logic of the chip may be supplied to an input A of the driver
10
. An output enable signal that controls data output from the output driver
10
may be supplied to a control input EN of the driver
10
.
A NOR gate
12
may be arranged for driving the pull-up transistor P
1
. The NOR gate
12
may have its inputs connected to the inputs A and EN, and its output couples to the gate of the transistor P
1
. The output enable signal may be supplied to the NOR gate
12
via an inverter
14
.
a NAND gate
16
that drives the pull-down transistor N
1
receives the data signal from the input A and the output enable signal from the control input EN. The output signal of the NAND gate
16
is supplied to the gate of the transistor N
1
.
An output node O provided at the junction between the transistors P
1
and N
1
may be connected to an output pin of a controller chip, for example, to an interrupt pin for supplying interrupt signals to an external CPU. The totem-pole driver
10
is a tri-state device. Its output may be driven high, low, or to a high-impedance state.
The data output from the output driver
10
may be enabled when the output enable signal at the EN input is at a logic 1 level. When the data output is enabled, the output signal of the output driver
10
is driven high in response to a high level at the data input IN, and is driven low in response to a low level at the data input IN. When the output enable signal is at a logic 0 level, the output driver
10
is in a high-impedance state, and the data output is disabled.
Referring to
FIG. 2
, an exemplary open-drain output driver
20
for driving an output of a chip may comprise a single N-type MOS transistor N
2
coupled between an output node O and a ground terminal. The transistor N
2
is driven by a NAND gate
22
coupled to a data input A for receiving a data input signal from internal logic of the chip, and to a control input EN supplied with an output enable signal for enabling data output.
By contrast with the totem-pole driver
10
, the open-drain driver
20
has two states. When its data output is enabled by the output enable signal, the open-drain output driver
20
drives the output low in response to a low level of a data input signal supplied from internal logic circuitry. However, when the data input is at a high level, the open-drain driver
20
is switched into a high-impedance state. If the data output is disabled, the open-drain driver
20
is maintained in a high-impedance state regardless of the data input level.
As illustrated in FIG.
3
(
a
), the totem-pole output driver
10
may drive an output interrupt pin
30
of a controller to supply an interrupt signal to an input interrupt driver
40
of an external CPU via its input interrupt pin
50
. The totem-pole driver may be used to send an interrupt produced by a single controller to the CPU.
The advantage of an open-drain output driver over a totem-pole output driver is in providing a user with ability to perform an OR logical operation for interrupts produced by multiple controllers. Referring to FIG.
3
(
b
), the open-drain output drivers
20
-
1
,
20
-
2
,
20
-
n
allow a user to combine interrupts supplied from interrupt pins
30
-
1
,
30
-
2
,
30
-
n
of n controllers interacting with the CPU in a communications system. An interrupt signal produced at any one of the interrupt pins
30
-
1
,
30
-
2
,
30
-
n
will be transmitted to the input interrupt driver
40
of the CPU via the input pin
50
. An external resistor
60
may be used to provide an interrupt interface.
Thus, to enable a user to provide interrupts from a single controller or to combine interrupts from multiple controllers, separate interrupt pins should be arranged on a controller chip for driving interrupts in a totem-pole drive mode and in a open-drain drive mode. However, it would result in increasing the total number of pins on the chip.
To produce interrupt signals in totem-pole and open-drain drive modes without increasing the number of interrupt pins, it would be desirable to provide a control circuit that allows a totem-pole output driver to function as an open-drain output driver.
DISCLOSURE OF THE INVENTION
Accordingly, a primary object of the present invention is to provide a system for enabling a user to configure a totem-pole driver to operate in an open-drain drive mode.
The above and other advantages of the invention are achieved, at least in part, by providing an output driver for driving an output pin on a chip. The output driver comprises a totem-pole driver coupled to the output pin. A control circuit is coupled to a control input of the totem-pole driver for configuring the driver to operate in an open-drain drive mode when a mode control signal has a first logic value, and for configuring the driver to operate in a totem-pole drive mode when the mode control signal has a second logic value.
In accordance with a preferred embodiment of the present invention, the control circuit may comprise a first gate circuit having a first input supplied with a data input signal representing data to be supplied from the output pin, and a second input supplied with the mode control signal. A second gate circuit may have a first input coupled to the output of the first gate circuit via an inverter. A second input of the second gate circuit may be supplied with an output enable signal. The output of the second gate circuit may be coupled to the control input of the totem-pole driver. The mode control signal may be programmed by a user.
In accordance with one aspect of the invention, the output driver may be used for driving an interrupt request output in a PCI interface.
In accordance with a method of the present invention, the following steps are carried out for controlling an output driver:
supplying the output driver with a first mode control signal for maintaining the output driver in a totem-pole drive mode, and
supplying the output driver with a second mode control signal for switching the output driver into an open-drain drive mode.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5519345 (1996-05-01), Farrell et al.
patent: 5530379 (1996-06-01), Konishi et a
Haubursin Pierre
Yu Ching
Advanced Micro Devices , Inc.
Le Don Phu
Santamauro Jon
Young & Thompson
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