Method and system for supporting multiple cache configurations

Details Method and system for supporting multiple cache configurations Method and system for supporting multiple cache configurations

2006-05-23

2006-05-23

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S118000, C711S129000, C711S173000

Reexamination Certificate

active

07051179

ABSTRACT:
A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

REFERENCES:
patent: 5014195 (1991-05-01), Farrell et al.
patent: 6606686 (2003-08-01), Agarwala et al.
patent: 6760272 (2004-07-01), Franz et al.

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