Method and system for supporting multiple cache configurations

Details Method and system for supporting multiple cache configurations Method and system for supporting multiple cache configurations

2000-12-07

2004-07-06

Peikari, B. James (Department: 2186)

Static information storage and retrieval

Addressing

Multiple port access

C711S104000, C711S001000

Reexamination Certificate

active

06760272

ABSTRACT:

BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, an electrical coupling network between a static random access memory
20
a
(hereinafter “SRAM
20
a
”) and a static random access memory
20
b
(hereinafter “SRAM
20
b
”) is shown. SRAM
20
a
and SRAM
20
b
are identical memory devices. Specifically, both SRAM
20
a
and SRAM
20
b
have an identical pin arrangement including seven (7) rows and seventeen (17) columns of pins. The first column of pins are shown in FIG.
1
. In the first column of pins, SRAM
20
a
includes two (2) output power supply pins
21
a
and
27
a
, and SRAM
20
b
includes two (2) output power supply pins
21
b
and
27
b
. Also in the first column of pins, SRAM
20
a
includes four (4) synchronous address input pins
22
a
,
23
a
,
25
a
, and
26
a
, and SRAM
20
b
includes four (4) synchronous address input pins
22
b
,
23
b
,
25
b
, and
26
b
. Pin
24
a
of SRAM
20
a
and pin
24
b
of SRAM
20
b
are not utilized.
In support of four (4) cache configurations, SRAM
20
a
is mounted to a front side of a processor card
10
, and SRAM
20
b
is mounted to a rear side of processor card
10
. SRAM
20
a
and SRAM
20
b
are positioned with an alignment of pin
21
a
and pin
27
b
, an alignment of pin
22
a
and pin
26
b
, an alignment of pin
23
a
and pin
25
b
, an alignment of pin
24
a
and pin
24
b
, an alignment of pin
25
a
and pin
23
b
, an alignment of pin
26
a
and pin
22
b
, and an alignment of pin
27
a
and pin
21
b.
Pin
22
a
and pin
22
b
are functionally equivalent and electrically coupled via a conductor
28
a
within processor card
10
to concurrently receive a first address bit signal from a microprocessor. Pin
23
a
and pin
23
b
are functionally equivalent and electrically coupled via a conductor
28
b
within processor card
10
to concurrently receive a second address bit signal from the microprocessor. Pin
25
a
and pin
25
b
are functionally equivalent and electrically coupled via a conductor
28
c
within processor card
10
to concurrently receive a third address bit signal from the microprocessor. Pin
26
a
and pin
26
b
are functionally equivalent and electrically coupled via a conductor
28
d
within processor card
10
to concurrently receive a fourth address bit signal from the microprocessor. The four (4) address bits signal are selectively provided by the microprocessor as a function of a selected cache configuration.
A drawback associated with the aforementioned electrical couplings as shown is the length of conductors
28
a
-
28
d
tends to establish a maximum frequency at which the microprocessor can effectively and efficiently control SRAM
20
a
and SRAM
20
b
, and the established maximum frequency can be significantly lower than a desired operating frequency of the microprocessor. The computer industry is therefore continually striving to improve upon the electrical coupling between the synchronous address input pins of SRAM
20
a
and SRAM
20
b
whereby a maximum frequency at which a microprocessor can effectively and efficiently control SRAM
20
a
and SRAM
20
b
matches a desired operating frequency of the microprocessor. The computer industry is also continually striving to improve upon the electrical communication of a selected cache configuration from a microprocessor to the synchronous address input pins of SRAM
20
a
and SRAM
20
b.
FIELD OF THE INVENTION
The present invention generally relates to computer hardware mounted upon a processor card, and in particular to an electrical coupling between memory components for supporting multiple cache configurations and an electrical communication from a microprocessor to the memory components for selecting one of the supported multiple cache configurations.
SUMMARY OF THE INVENTION
One form of the present invention is a processor card having a first memory device and a second memory device mounted thereon. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The first address pin of the first memory device and the fourth address pin of the second memory device are electrically coupled to thereby concurrently receive a first address bit signal. The second address pin of the first memory device and the third address pin of the second memory device are electrically coupled to thereby concurrently receive a second address bit signal.
Another form of the present invention is a system including a first memory device, a second memory device, and a microprocessor. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The microprocessor is operable to concurrently provide a first address bit signal to first address pin of the first memory device and the fourth address pin of the second memory device. The microprocessor is further operable to concurrently provide a first address bit signal to second address pin of the first memory device and the third address pin of the second memory device.
The foregoing and other features and advantages of the invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof.


REFERENCES:
patent: 4872091 (1989-10-01), Maniwa et al.
patent: 5126822 (1992-06-01), Salters et al.
patent: 5262990 (1993-11-01), Mills et al.
patent: 5280590 (1994-01-01), Pleva et al.
patent: 5574682 (1996-11-01), Shinohara
patent: 5980093 (1999-11-01), Jones et al.
patent: 6078536 (2000-06-01), Moon et al.
patent: 6438625 (2002-08-01), Olson

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