Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-12-18
2000-10-24
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
348 7, 711169, 711114, 711112, G06F 1200, H04N 710
Patent
active
061382213
ABSTRACT:
In a system 100, such as a video-on-demand-server, a reader 180 reads data from a storage medium 110 and stores the read data in buffers 125. The data is supplied from the buffers 125 to users 130 for consumption in the form of a plurality of data streams. The data streams may be fixed rate or variable rate with an identical maximum consumption rate of R.sub.max data elements per second. The reader 180 is controlled by a scheduler 170. The scheduler 170 divides a predetermined period of t.sub.cycle seconds, wherein for each active data stream at least R.sub.max *t.sub.cycle data elements can be read from the storage medium, into n successive time intervals, each of t.sub.interval seconds. For each data stream a corresponding buffer 125 is reserved for storing at least R.sub.max *(n+1)*t.sub.interval data elements. The data is read from the storage medium 110 by repeatedly sweeping the storage medium 110 for a group of data streams. Immediately before causing the reader 180 to perform a next sweep, the scheduler 170 determines the composition of the next group of data streams to be supplied with data. At least data streams whose corresponding buffer 125 comprise less then R.sub.max *2*t.sub.interval data elements are assigned to this group.
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PHN 15,381, Serial No. 08/678,217.
Korst Johannes H. M.
Lawerman Edzer
Pronk Serverius P. P.
Van Doren Giel
Bataille Pierre-Michel
Cabeca John W.
Piotrowski Daniel J.
U.S. Philips Corporation
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