Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-10-23
1998-09-15
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711168, 395855, G06F 1208, G06F 1328
Patent
active
058095373
ABSTRACT:
A method and system for simultaneous retrieval of snoop address information in conjunction with the retrieval/storing of a cache line load/store operation. The method and system are implemented in a data processing system comprising at least one processor having an integrated controller, a cache external to the at least one processor, and an interface between the at least one processor and the external cache. The external cache includes a tag array and a data array. Standard synchronous static Random Access Memory (RAM) is used for the tag array, while synchronous burst made static RAM is used for the data array. The interface includes a shared address bus, a load address connection and an increment address connection. A cache line load/store operation is executed by placing an address for the operation on the shared address bus, and latching the address with the external cache using a signal from the load address connection. Thereafter, the latched address is incremented in response to a signal from the increment address connection. This allows the shared address bus to be used for execution of snoop operations simultaneously with the retrieval/storage of a cache line load/store operation.
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Itskin Randall Clay
Pescatore, Jr. John Carmine
Qureshi Amjad Z.
Ruth David Brian
Bragdon Reginald G.
Henkler Richard A.
International Business Machines Corp.
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