Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2011-08-02
2011-08-02
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S132000
Reexamination Certificate
active
07992125
ABSTRACT:
Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.
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Cadence Design Systems Inc.
Chiang Jack
Schwegman Lundberg & Woessner, P.A.
Tat Binh C
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