Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-03-13
2007-03-13
Shah, Kamini (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S014000, C703S018000, C702S059000, C702S060000, C702S064000, C702S070000, C702S079000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10322089
ABSTRACT:
A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device. One or more short-circuit current points can be determined from the model and used to generate a polygonal waveform model of the short-circuit current, or can be used along with the width (period) of the waveform to calculate short-circuit power dissipation directly.
REFERENCES:
patent: 5453991 (1995-09-01), Suzuki et al.
patent: 5835380 (1998-11-01), Roethig
patent: 5923712 (1999-07-01), Leyendecker et al.
patent: 5933358 (1999-08-01), Koh et al.
patent: 6066177 (2000-05-01), Hatsuda
patent: 6209122 (2001-03-01), Jyu et al.
patent: 6405348 (2002-06-01), Fallah-Tehrani et al.
patent: 6731129 (2004-05-01), Belluomini et al.
patent: 6975978 (2005-12-01), Ishida et al.
patent: 2002/0016950 (2002-02-01), Sakamoto
patent: 2002/0042704 (2002-04-01), Najm et al.
patent: 2002/0065643 (2002-05-01), Hirano et al.
patent: 2002/0174409 (2002-11-01), Cohn et al.
patent: 2002/0183990 (2002-12-01), Wasynczuk et al.
patent: 2003/0070150 (2003-04-01), Allen et al.
patent: 2003/0189865 (2003-10-01), Ausserlechner et al.
patent: 2004/0113680 (2004-06-01), Dray
patent: 2004/0158809 (2004-08-01), Kashimoto et al.
patent: 2006/0225009 (2006-10-01), Reddy et al.
Anas A. Hamoui, and Nicholas C. Rumin, An Analytical Model for Current, Delay, and Power Analysis of Submicron CMOS Logic Circuits,Oct. 2001,IEEE,vol. 47,No. 10,pp. 999-1007.
Anas A. Hamoui, and Nicholas C. Rumin, “An Analytical Model for Current, Delay, and Power Analysis of Submicron CMOS Logic Circuits”, IEEE Transactions on Circuits and Systems, vol. 47, No. 10, Oct. 2000, pp. 999-1007.
E. Acar, R. Arunachalam, and S. R. Nassif, “Predicting Short Circuit Power From Timing Models”, Nov. 14, 2002, total pages of 6.
Acar Emrah
Arunachalam Ravishankar
Nassif Sani Richard
Gebresilassie Kibrom
Harris Andrew M.
Mitch Harris Atty at Law, LLC
Salys Casimer K.
Shah Kamini
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