Method and system for shape processing within an integrated circ

Details Method and system for shape processing within an integrated circ Method and system for shape processing within an integrated circ

1996-10-07

2000-07-11

Voeltz, Emanuel Todd

Boots, shoes, and leggings

G06F 1750

Patent

active

060862386

ABSTRACT:
A method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation is disclosed. In accordance with the method and system of the present invention, a set of coordinates of an overlapping region formed by at least one interconnect is first identified. Subsequently, each metal layer present within the overlapping region is classified. Each interconnect edge present on each side of the overlapping region is then determined. Finally, a neighbor in a direction perpendicular to each side of the overlapping region is determined. By so doing, the parasitic capacitance between the overlapping region and its determined neighbors can be evaluated.

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