Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-12-29
2002-12-24
Lane, Jack A. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000
Reexamination Certificate
active
06499085
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer systems, and in particular, to a method and a corresponding system for servicing memory access requests.
2. Description of the Related Art
In computer systems, instructions and data required by a requesting agent (e.g., processor or an input/output (I/O) device) may be retrieved from a main memory or other storage device. However, the latency involved with retrieving information from the main memory can impose a burden on system performance. To improve system performance, prefetching techniques may be implemented to prefetch instructions/data into a faster memory device prior to the time the instruction/data is requested by the requesting agent. In some implementations, the faster memory device may be located external to the requesting agent so that the faster memory device can be loaded without effecting the bandwidth of a bus coupling the requesting agent to the rest of the computer system.
Typically, processors are configured to implement cache line size transfers. Due to demand for faster and more powerful computer systems, processors capable of supporting a larger cache line size are being developed and produced. For example, some conventional processors are configured to support 32-byte cache lines, while some recently developed processors are capable of supporting 64-byte cache lines. Components of a computer system such as I/O devices may be configured to support a certain cache line size.
Situations may arise in which the cache line size supported by a computer component is different from the cache line size supported by a processor, resulting in a cache line size mismatch. For example, a computer component (e.g., I/O controller, I/O devices) may be configured to implement a certain cache line size transfer (e.g., 32 bytes), perhaps, because it was developed for use with a processor supporting a 32 byte cache line scheme. If such component is coupled to a processor utilizing a larger cache line size (e.g, 64 bytes), partial cache line memory requests (e.g., 32 byte data request) from such component may result in additional snoop requests occurring on the processor bus due to mismatch in cache line sizes, wasting the processor bus bandwidth and reducing overall system performance.
REFERENCES:
patent: 5845101 (1998-12-01), Johnson et al.
patent: 6138213 (2000-10-01), McMinn
patent: 6367006 (2002-04-01), Tran
Acharya Satish
Bogin Zohar
Harriman David J.
Wirkus Zdzislaw A.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lane Jack A.
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