Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-07-30
2003-06-24
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S102000
Reexamination Certificate
active
06584553
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to programming data into memory on packaged integrated circuits (ICs) on an automated system, and more particularly to reducing the time required to program a plurality of such ICs.
BACKGROUND OF THE INVENTION
Various functions including memory storage can be implemented on a single integrated circuit (IC) that is programmed and then packaged. In many applications, it is necessary to program or store data in memory on such ICs after packaging has occurred. Various pin-out connections from the memory to package pins are provided and data may be programmed into the memory using various systems that preferably are automated.
FIG. 1A
depicts a prior art system
10
for programming data into a plurality of memory containing ICs
20
-
1
,
20
-
2
,
20
-
x.
System
10
includes a pick-up head
30
that can move in three dimensions (x,y,z) along a gantry
40
that is part of a handler
50
. The pick-up head can take an IC from an in-tray
60
containing unprogrammed ICs, and manipulate and insert that IC into a socket
70
-
x
on a single programmer
80
associated with system
10
. After successful programming of data, the ICs are again manipulated by pick-up head
30
and placed in an out-tray
90
.
FIG. 1A
also depicts the x,y,z axis associated with the system.
Data is programmed into the ICs in blocks, where the total number of blocks of data is determined by the size of the memory to be programmed. ICs containing large storage memory will thus be programmed with a large number of blocks of data. Thus, one function of programmer
80
is to program the data blocks to be stored into memory in the ICs in the sockets of the programmer.
In the prior art system shown in
FIG. 1A
, each socket
70
-
x
in the programmer
80
is loaded with an IC
20
-
x
to be programmed, and the identical programming cycle step is carried out in each IC simultaneously. A typical system
10
operation cycle includes an insertion check step, an erase step, a programming step, a verification step, and a security check step.
Thus, in a lock-step system such as system
10
, each IC is inserted into the programmer simultaneously, each IC memory is erased simultaneously, and is then programmed with the same block of data simultaneously, and each programmed IC is then verified simultaneously. Finally, a security check is then carried out on all ICs simultaneously. After the first block of data has been successfully programmed into each memory, programmer
80
can start to program the next block of data into each IC, and so forth until all blocks of data have been loaded into each IC.
While the above described parallel operation may sound efficient, it is important to appreciate that most of the system
10
cycle time is occupied while programming the data. The remaining cycle tasks occupy relatively little time. The insertion portion of a cycle involves confirming correct orientation of the inserted IC with respect to the socket on the programmer, a task rapidly carried out. But programming is quite slow in that much data in a block is required to be written to memory for each IC, each IC being simultaneously programmed with the same block of data. Once the block of data has been programmed into each IC, the step of verifying that the data block was correctly programmed into memory can be carried out quite rapidly. A security check typically involves reading but a few bits of data and is also carried out quite rapidly. ICs that have been verified as being programmed are then manipulated by pick-up head
30
and placed in the out-tray
90
. The out-tray can then be removed and the ICs that have been successfully programmed can be taken elsewhere, for example for insertion into a printed circuit board.
An advantage of system
10
is that a common set of programming electronics is wired to each socket in the programmer, which can represent a cost savings in the manufacture of system
10
. Further, the individual sockets can be more densely packed, which means the overall size of the programmer unit can be reduced. But a main disadvantage associated with the parallel nature of prior art system
10
is that one must first wait for all sockets to be loaded, and then wait a substantial fraction of a system cycle for programming of the same data block to occur for each IC. During these relatively long time periods, little else can occur within system
10
.
Prior art system
10
′ shown in
FIG. 1B
attempts to reduce the relatively long dead time periods noted in the configuration of
FIG. 1A
by introducing asynchronous operation into the system. In system
10
′, a separate programmer
80
-
x
is provided for each socket
80
-
x
into which a memory containing IC
20
-
x
can be inserted by pick-up head
30
for programming with blocks of data by the associated programmer.
In the configuration of
FIG. 1B
, as soon as pick-up head
30
has retrieved IC
20
-
1
from in-tray
60
and has inserted IC
20
-
1
into socket
70
-
1
, and proper insertion has been confirmed, the associated programmer
80
-
1
can begin programming the first block of data into the IC memory. After the data has been programmed, verification and security checks are carried out on IC
20
-
1
. Once pick-up head
30
has corrected seated IC
20
-
1
into socket
70
-
1
, the pick-up head can retrieve IC
20
-
2
and insert this IC into socket
70
-
2
, and as soon as insertion is confirmed, the separate programmer
80
-
2
associated with socket
70
-
2
can begin programming IC
20
-
2
, and so on.
While system
10
′ offers the advantage of asynchronous programming of the various ICs, it will be appreciated that a plurality of programmer units
80
-
x
must now be provided, one programmer unit per an associated socket
70
-
x.
Each programming site or socket can operate independently without having to wait until every socket is loaded with an IC or unloaded with a programmed (or rejected) IC. But having to provide a plurality of programmers adds expense to the overall system. Further, it is generally required that each socket
70
-
x
be spaced somewhat farther apart than in the configuration of FIG.
1
A.
What is needed then is a programming system that can operate more rapidly than prior art synchronous parallel systems, but without requiring a separate dedicated programmer unit for each programming site.
The present invention provides such a programming system, and a method of programming with such system.
SUMMARY OF THE INVENTION
The present invention provides a programming system that includes a single programmer with multiple programming sites or sockets that can be densely packed on the programmer. The data to be programmed into each IC in a socket in the programming system is broken down into a number of blocks that are programmed into each IC in a segmented sequence. The number of blocks of data to be programmed into an IC is equal to X where X preferably is the number of programming sites or IC sockets in the programming system. Thus if the size of the data to be programmed is Q, each block of data represents the Q/X.
The system pick-up head obtains the first IC, typically from an in-tray, and inserts the first IC into the first programming socket, where it is insertion-checked and programmed with only the first block of data to be stored. The pick-up head then inserts the second IC into the second programming socket where it is insertion-checked and the first and second IC are now simultaneously programmed with the second block of data, whereupon the first IC will now contain two data blocks, and the second IC will contain one data block. The pick-up head inserts the third IC into the third programming socket where it is insertion-checked and the first, second, and third IC are simultaneously programmed with only the third data block, whereupon the first IC now is programmed with three data blocks, the second IC with two data blocks, the third IC with one data block.
The above cycle is repeated a number of times, typically equal to X, until the fir
Dorsey & Whitney LLP
Exatron, Inc.
Verbrugge Kevin
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