Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
1999-11-03
2002-01-29
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S113000, C326S115000, C327S287000
Reexamination Certificate
active
06342793
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain and, in particular, to a method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain on the same chip without detrimental noise transmission into the quiet power domain.
2. Description of the Related Art
In mixed signal designs having large amounts of CMOS logic, generally any CMOS control signals that need to connect and feed to circuitry in a quiet analog power domain are converted to low level differential signals before being used therein. Furthermore, any switching CMOS circuitry in the analog power domain must be kept to a minimum and somewhat isolated so that switching noise is not introduced onto the quiet analog power supply. Another concern in these mixed signal designs is the transmission of noise on the noisy logic power supply to the quiet power supply.
Problems occur for these designs when a large number, such as one hundred (100) or more, CMOS control signals need to be used in the analog power domain. Converting such a large number of signals to differential signals in the traditional way while also maintaining a small chip size is not at all practical. For example, such a conversion would require as many CMOS switching circuits in the analog power domain as signals to be converted, thus introducing a large amount of switching noise to the quiet analog power domain.
With reference now to the figures and in particular with reference to
FIG. 1
, a traditional or conventional prior art CMOS conversion multiplexer
10
that is used for converting CMOS signals to differential signals is shown. The CMOS conversion multiplexer
10
comprises various bipolar transistors
12
, various field effect transistors (FETs)
14
, a CMOS inverter
16
, constant current sources
18
, and various resistors
20
coupled together in the manner shown in
FIG. 1. A
power supply voltage VDD1
24
is applied to the multiplexer
10
, and the multiplexer
10
is grounded at GND1
25
for proper operation of the multiplexer.
The general operations of multiplexer
10
is described as follows: The CMOS signal is sent into the multiplexer
10
at CMOS input signal
15
. A CMOS signal is defined as a signal whose low level is 0V and its high level is the power supply. The signal A
2
is in the analog part of the domain. If A
2
is high, then the CMOS signal turns on the transistor Q
9
and the collector of Q
9
is pulled low. If A
2
is low, then the CMOS signal turns on the transistor Q
10
and the collector of Q
10
is pulled low. Transistors Q
9
and Q
10
are a current steering differential pair meaning that the current through the current source is constant and either goes through Q
9
or Q
10
depending on the value of A
2
. The base of Q
9
is either driven to the voltage value of VDD1 when it is on or is clamped by Q
3
to 1 diode below VDD1 when it is off. Meanwhile, the base of Q
10
is connected to a voltage divider whereas the base is held to a constant voltage that is a 1/2 diode below VDD1. The generally noisy input signal
15
is converted to low voltage level differential signals by the converter portion
10
A of the circuit. Low level differential or ECL signals can be defined as two signals whose amplitude is small, for example 300 mV, and whose phase relationship is such that one is at its low voltage while the other is at its high voltage. This phase relationship is sometimes called
180
degrees out of phase. The outputs of the converter circuit
10
A are used as inputs to the differential multiplexer
10
B called MA and MB. When MB is high the ECL inputs B
0
and B
1
are transferred to the ECL Differential Outputs and when MA is high the ECL inputs A
0
and A
1
are transferred to the ECL Differential Outputs. For example, this could be a method by which a designer could use a control loop to choose dynamically between two delays of differing values. A
0
, A
1
is chosen by the multiplexer
10
when A
2
is high, and B
0
, B
1
is chosen by the multiplexer
10
when A
2
is low. Thus, the CMOS conversion multiplexer
10
chooses between two values in a control loop.
One problem with conversion multiplexer
10
is that it requires accurate current sources
18
and careful layout. Another problem is that it requires the CMOS signal to be referenced in the quiet power supply by using at least one CMOS inverter. Furthermore, for processing a large amount of signals, a conversion multiplexer
10
would be required for each signal to be converted. The current mirrors required for that many circuits would require a large amount of chip area. Also, the conversion of CMOS signals to differential signals is performed in a multiplexer
10
, which is able to be viewed as one, single stage of circuits, but it requires a large amount of area, careful control of current and would inject switching noise on the quiet power supply by means of the CMOS inverter
16
. At least one CMOS inverter for each signal to be converted is required on the quiet power supply. The injection of noise onto the quiet power supply is a means by which, for example, an accurate delay could be undesirably modulated.
With reference now to the figures and in particular with reference to
FIG. 2
, another CMOS conversion multiplexer
11
is shown. The multiplexer
11
is used to attempt to accomplish the conversion of CMOS logic signals into differential signals. The multiplexer
11
further comprises various bipolar transistors
12
, various FETs
14
, a current source
18
, and various resistors
20
coupled in the manner shown in FIG.
2
. Parasitic capacitance
26
are shown to exist at the various areas in FIG.
2
. Also, power supply voltage VDD1
24
is used to drive the multiplexer
11
, and the multiplexer
11
is coupled to ground GND1
25
for proper operations of the multiplexer
11
.
The general operations of the multiplexer
11
is described as follows: The current source
18
provides a constant accurate current source for the multiplexer. The CMOS input signal is sent in as the MB signal which is inputted to the PFET T
0
while the complimentary CMOS input signal (180 degrees out of phase from the CMOS input signal) is sent in as the MA which is inputted to the PFET T
1
. As stated earlier, the MA and MB signals will be relatively noisy signals. The PFET T
0
provides an A-Select signal while the PFET T
1
provides a B-Select signal. The PFETs T
0
and T
1
are driven from 0 to VDD1 with what are considered CMOS control signals. The transistors
12
are driven by the ECL low level differential signals
28
. However, parasitic capacitances exist from the gate to the drain and the gate to the source of the PFETs T0 and T1. Parasitic capacitances also exist from the base to the emitter and the base to the collector of the bipolar transistors Q
4
and Q
5
. The parasitic capacitances provides paths to communicate noise from power supplies that have a lot of switching noise on them and logic power supplies. CMOS signals look like CMOS input signal
15
in FIG.
3
. differential signals
28
. However, parasitic capacitances exist from the gate to the drain and the gate to the source of the PFETs T
0
and T
1
. Parasitic capacitances also exist from the base to the emitter and the base to the collector of the bipolar transistors Q
4
and Q
5
. The parasitic capacitances provides paths to communicate noise from power supplies that have a lot of switching noise on them and logic power supplies. CMOS signals look like CMOS input signal
15
in FIG.
3
.
If the CMOS input signal
15
is connected directly to converter inputs MB and MA, the noise that is coupled to the outputs P
10
, P
11
was unacceptable even though the design was compact and simple. Also to prevent problems that could be caused by ground shift between the two power domains, the incoming CMOS signals should be referenced to the analog power supplies to ensure full switching of the PFET. Th
Lukes Eric John
Strom James David
Woeste Dana Marie
Bracewell & Patterson LLP
International Business Machines - Corporation
Paik Steven S.
Tokar Michael
LandOfFree
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