Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-26
2002-08-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C702S084000
Reexamination Certificate
active
06434725
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor testing, and more particularly, to a method for analyzing test results for test failure data to correlate failures to physical processes.
2. Description of the Related Art
Semiconductor testing is typically performed by generating a data test pattern of 1's and 0's. The pattern may be scrambled by altering addresses of the data to be stored in a memory array. Then, the data is retrieved from the memory array and compared to the original data. Any discrepancies of data are considered a fail. Otherwise, the tested cells pass. The test results are then output and stored to create, for example, a bit map. The data output is typically compressed data. In other words, pass/fail (1 or 0) results are output and logically combined to reduce the data set. Once all the data is available for a given semiconductor wafer, a yield value is assigned to the wafer to designate its overall quality. Yield is often expressed as a percentage designated by devices, which passed testing, divided by a total number of devices tested (times 100).
Yield provides a single value, which describes the quality of a wafer (or chip) and gives a level of confidence for the reliability of a given wafer. However, yield is one-dimensional and fails to provide insight as to why failures have occurred. Yield problems are in general not easy to be correlated to a root cause. A mathematical correlation between failures and yield is difficult.
In some instances, an assumption may made that yield is down due to the identification of failures by a particular test. Correlating the fail count to a certain parameter may result in changes that reduce the fail count for that particular test, but may also cause a different test to pick up more fails.
Therefore, a need exists for a correlation parameter, which provides information about the quality of a chip while also indicating a root cause for failures.
SUMMARY OF THE INVENTION
A method for yield correlation for semiconductor chips, in accordance with the present invention, includes providing test data for a plurality of tests on each of a plurality of semiconductor chips. A global parameter is assigned to each chip as a quality measure based on the test data for that chip. Values for a plurality of parameter classes are determined, and each parameter class represents a parameter measured for each chip tested. A correlation between the values of the parameter classes and the global parameter values for the plurality of chips is then determined. The correlation for each of the parameter classes is compared to identify at least one parameter class, which detracts from chip yield.
A method for yield correlation for semiconductor chips, in accordance with the invention, includes providing test data for a plurality of tests on each of a plurality of semiconductor chips. A global parameter is assigned to each chip as a quality measure based on the test data for that chip and based on failures and measurements made for each chip. Values for a plurality of parameter classes are determined, and each parameter class represents a parameter measured for each chip tested. A single value is provided for each parameter class for each chip, and a correlation between all of the single values of the parameter classes for each chip and the global parameter values for each chip of the plurality of chips is determined. The correlation for each of the parameter classes are compared to identify at least one parameter class which detracts from chip yield. Processes are identified which are responsible for yield detraction based on the at least one parameter class.
In other methods, the step of assigning a global parameter to each chip may include the step of analyzing the test data for all the tests to determine the global parameter for each chip. The step of assigning a global parameter to each chip may include the steps of assigning an initial global parameter based on test results of one test and modifying the initial global parameter based on test results of other tests. The step of assigning a global parameter to each chip may include the step of employing a mathematical formula for calculating the global parameter.
In still other methods, the step of assigning a global parameter to each chip may include the step of considering the severity of test results to modify the global parameter. The step of assigning a global parameter to each chip may include the step of weighting the global parameter based on a test type. The step of determining values for a plurality of parameter classes may include measuring parameters on each chip and combining the measured parameters into a single number. The step of determining a correlation between the values may include the step of computing a correlation coefficient for each parameter class. The method may further include the step of eliminating from consideration parameter classes having the correlation coefficient less than a threshold value.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
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Broach Larry
Lammering Herbert
Sommer Michael Bernhard
Braden Stanton
Infineon Technologies Richmond LP
Rossoshek Helen
Smith Matthew
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