Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-09-30
2010-02-23
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07669158
ABSTRACT:
A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.
REFERENCES:
patent: 6009250 (1999-12-01), Ho et al.
patent: 6011911 (2000-01-01), Ho et al.
patent: 6249904 (2001-06-01), Cobb
patent: 6253364 (2001-06-01), Tanaka et al.
patent: 6301697 (2001-10-01), Cobb
patent: 6370679 (2002-04-01), Chang et al.
patent: 6467076 (2002-10-01), Cobb
patent: 6505327 (2003-01-01), Lin
patent: 6560766 (2003-05-01), Pierrat et al.
patent: 6735742 (2004-05-01), Hatsch et al.
patent: 6757876 (2004-06-01), Habitz
patent: 6865726 (2005-03-01), Igusa et al.
patent: 6951004 (2005-09-01), Kamon
patent: 2002/0199157 (2002-12-01), Cobb
Rieger, Michael L. et al., “OPC strategies to minimize mask cost and writing time,” 21st annual BACUS Symposium on Photomask Technology, Proceedings of SPIE vol. 4562, pp. 154-160, 2002.
Rieger, Michael L, et al, “Anticipating and controlling mask costs within EDA physical design,” Proceedings of SPIE, vol. 5130, pp. 617-627, 2003.
Cadence Design Systems Inc.
Chiang Jack
Sheppard Mullin Richter & Hampton LLP
Tat Binh C
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