Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-24
2001-01-16
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06175949
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuit design tools and, more particularly, to a system and method for selecting sizes of components for integrated circuits.
2. Description of the Related Art
The design of integrated circuits, for example very large scale integration (VLSI) circuits may be very time consuming and labor intensive. Many iterations are performed before a chip design is completed. The iterations required of chip designers often includes the following procedure:
1. Choose the logic and topology of the circuit to be designed.
2. Choose the initial sizes of the transistors and/or components to attempt to obtain the desired target performance of the circuit to be designed. This selection process typically involves an extensive visual inspection of the circuit and many hand calculations by the designer.
3. Run timing verification using computer aided design tools on the circuit to verify that the circuit has met its target performance.
4. If the desired target performance is not met, adjust the component, for example a transistor, sizes based on the timing results and repeat step 3. The adjustment of the component sizes in this step also includes an extensive visual inspection of the circuit and many calculations that are often performed by hand.
5. If it is not possible to meet the desired target performance using steps 3-4, alter the circuit topology and repeat steps 2-4. In addition, the designer needs to be able to obtain early estimates of circuit performance such that decisions can be made as early as possible as to whether a change in the circuit topology is essential to improve performance.
Steps 2 through 4 may be referred to as tuning steps for “tuning” the circuit. The conventional method as described above tends to be very time consuming and labor intensive. The conventional method usually relies on calculating an RC network in order to evaluate the circuit since this technique lends itself more readily to hand calculations. Therefore, a need exists for an improved system and method for tuning an integrated circuit which provides early estimates of maximum performance and rapid selection of component sizes that meets or exceeds desired performance. A further need exists for providing a more user friendly design tool for analyzing integrated circuit designs.
SUMMARY OF THE INVENTION
A method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, selecting one or more objects to be sized, evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object and computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit.
In alternate methods, the step of outputting a topology with object sizes modified according to the associated equations may be included. The objects may include transistors, and capacitors and may further include the step of modeling the capacitors as transistors by adjusting a capacitance load of the capacitors in accordance with a capacitance conversion factor. The objects may further include hierarchical circuits, vectorized hierarchical circuits, and/or parameterized cells. The step of calculating node loads for analyzing the circuit in accordance with the user defined criteria may also be included. The physical constraints may include gain and the parameter may be a multiplier.
Another method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, locking one or more objects in the circuit to prevent sizing adjustment to locked objects thereby creating an unlocked subset of objects, evaluating cones of influence for the subset of objects to identify influenced objects influenced by a change in the selected object and computing for each of the subset of objects and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit.
In alternate methods, the step of outputting a topology with objects in the circuit having modified sizes may be included. The objects may include transistors, and capacitors and may further include the step of modeling the capacitors as transistors by adjusting a capacitance load of the capacitors in accordance with a capacitance conversion factor. The objects may further include hierarchical circuits and subcircuits, vectorized hierarchical circuits and/or parameterized cells. The step of calculating node loads for analyzing the circuit in accordance with the user defined criteria may also be included. The physical constraints include gain and the parameter may be a multiplier.
A system for automatically selecting object size in an integrated circuit includes a circuit topology having objects disposed therein, means for inputting equations associated with the objects to provide sizing adjustment for the objects, the equations including parameter values for one or more objects based on physical constraints of the circuit, means for selecting one or more objects to be sized, means for evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object and means for computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit.
In alternate embodiments, means for outputting a topology with objects in the circuit sized in accordance with the associated equations may be included. The objects may include transistors and capacitors and may further include a capacitance conversion factor for modeling capacitance loads as transistors. The objects may further include hierarchical circuits, vectorized hierarchical circuits and/or parameterized cells. The physical constraints may include values for a gain of the objects and the parameter may be a multiplier. The means for evaluating cones of influence for the objects may include a processor for analyzing the circuit to identify influenced objects.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
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Gristede George D.
Hwang Wei
Tretz Christophe Robert
F. Chau & Associates LLP
Garbowski Leigh Marie
International Business Machines - Corporation
Lintz Paul R.
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