Method and system for selecting and using source operands in...

Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S208000, C712S213000, C712S216000

Reexamination Certificate

active

06457118

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
The following applications, including this one, are being filed concurrently, and the disclosure of the other applications are incorporated by reference into this application in their entirety for all purposes:
U.S. patent application Ser. No. 09/410,633, entitled “AN INTEGER INSTRUCTION SET ARCHITECTURE AND IMPLEMENTATION”;
U.S. patent application Ser. No. 09/690,340, entitled “A METHOD FOR LOADING AND STORING DATA IN A COMPUTER SYSTEM”;
U.S. patent application Ser. No. 09/411,600, entitled “A FLOATING POINT INSTRUCTION SET ARCHITECTURE AND IMPLEMENTATION”.
U.S. patent application Ser. No. 09,410,675, entitled “A METHOD FOR ENCODING COMPUTER INSTRUCTION DATA FIELD”.
BACKGROUND OF THE INVENTION
The present invention relates generally to computer instruction set architectures, and particularly to the setting of selected operand fields.
In the past decade RISC (Reduced Instruction Set Computer) architectures, in which each instruction is ideally performed in a single operational cycle, have become popular. RISC architecture computers present several advantages over standard architecture computers. For instance, RISC instruction sets are capable of much higher data processing speeds due to their ability to perform frequent operations in shorter periods of time. The RISC devices began with 16-bit instruction sets, and grew to 32-bit instruction set architectures.
Pipelining techniques have been used in conjunction with RISC architectures to increase data throughput. Pipelining brought the need for data dependency checking; where the output of one instruction is the expected input into a following instruction. In some cases, instructions are divided into monadic (single source) and dyadic (dual source) instructions, each having its own unique dependency logic.
In addition to the complexities introduced by pipelining, applications have also contributed to the increasing complexity of RISC architectures. Frequently used constants, such as zero, can be set in different places from different sources.
Thus there is need for simplifying dependency logic without adding additional complexities to the hardware. In addition, there is a need to have a centralized, known source for zero to simplify the use of this frequently accessed constant.
SUMMARY OF THE INVENTION
According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to the present invention can be operative on a variety of computer architectures, including RISC architectures.
In a specific embodiment, the present invention provides a method for performing dependency checking on computer instructions in a pipeline of a computer system including determining if a first computer instruction has an opcode operating on only a first source operand. The computer instruction can have an opcode and a plurality of source operands, for example. Next, additional source operands can be replaced with the first source operand or the constant zero operand. Dependencies can be detected between the operands in the computer instruction and operands in other computer instructions in the pipeline. In a present embodiment, detecting can use the dyadic dependency checking for monadic instructions.
In another embodiment, the present invention provides a computer system for executing a computer instruction in a pipeline. The system can include a memory containing the computer instruction. The computer instruction can have a plurality of data fields, for example. A register that can return all zeros and a computer processor for executing the computer instruction stored in memory can also be part of the computer system. In a presently preferable embodiment, the register can be a 64-bit read only register, for example. The computer system can place one operand into the register while executing the computer instruction, for example.
Numerous advantages are provided by select embodiments according to the present invention. Embodiments can provide for setting selected operand fields in pipelined instructions for select computer architectures. In some embodiments, dependency checking for pipelined instructions can be provided. Many embodiments can be operable with RISC type computer architectures. Select embodiments can provide a standard hardware source for frequently used constant values and the like.
These and other advantages and features of the present invention will become apparent to those skilled in this art upon a reading of the following detailed description, which should be taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4306285 (1981-12-01), Moriya et al.
patent: 4814981 (1989-03-01), Rubinfeld
patent: 5251311 (1993-10-01), Kasai
patent: 5386565 (1995-01-01), Tanaka et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5434804 (1995-07-01), Bock et al.
patent: 5440705 (1995-08-01), Wang et al.
patent: 5448576 (1995-09-01), Russell
patent: 5452432 (1995-09-01), Macachor
patent: 5455936 (1995-10-01), Maemura
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5483518 (1996-01-01), Whetsel
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5530965 (1996-06-01), Kawasaki et al.
patent: 5570375 (1996-10-01), Tsai et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5596734 (1997-01-01), Ferra
patent: 5598551 (1997-01-01), Barajas et al.
patent: 5608881 (1997-03-01), Masumura et al.
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5657273 (1997-08-01), Ayukawa et al.
patent: 5682545 (1997-10-01), Kawasaki et al.
patent: 5682546 (1997-10-01), Garg et al.
patent: 5704034 (1997-12-01), Circello
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 5724549 (1998-03-01), Selgas et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5751621 (1998-05-01), Arakawa
patent: 5768152 (1998-06-01), Battaline et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5774701 (1998-06-01), Matsui et al.
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5781558 (1998-07-01), Inglis et al.
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 5832248 (1998-11-01), Kishi et al.
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5848247 (1998-12-01), Matsui et al.
patent: 5860127 (1999-01-01), Shimzaki et al.
patent: 5862387 (1999-01-01), Songer et al.
patent: 5867726 (1999-02-01), Ohsuga et al.
patent: 5884092 (1999-03-01), Kiuchi et al.
patent: 5896550 (1999-04-01), Wehunt et al.
patent: 5918045 (1999-06-01), Nishii
patent: 5930523 (1999-07-01), Kawasaki et al.
patent: 5930833 (1999-07-01), Yoshioka et al.
patent: 5944841 (1999-08-01), Christie
patent: 5950012 (1999-09-01), Shiell et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 5956477 (1999-09-01), Ranson et al.
patent: 5978874 (1999-11-01), Singhal et al.
patent: 5978902 (1999-11-01), Mann
patent: 5983017 (1999-11-01), Kemp et al.
patent: 5983379 (1999-11-01), Warren
patent: 6023757 (2000-02-01), Nishimoto et al.
patent: 6038582 (2000-03-01), Arakawa et al.
patent: 6038661 (2000-03-01), Yoshioka et al.
patent: 6091629 (2000-07-01), Osada et al.
patent: 6092172 (2000-07-01), Nishimoto et al.
patent: 6243732 (2001-06-01), Arakawa et al.
patent: 165 600 (1991-11-01), None
patent: 636 976 (1995-02-01), None
patent: 652 516 (1995-05-01), None
patent: 702 239 (1996-03-01), None
patent: 720 092 (1996-07-01), None
patent: 933 926 (1999-08-01), None
patent: 945 805 (1999-09-01), None
patent: 959 411 (1999-11-01), None
patent: 8320796 (1996-12-01), None
patent: 8329687 (1996-12-01), None
patent: 9212358 (1997-08-01), None
patent: 9311786 (1997-12-01), None
patent: WO 98/13759 (1998-04-01), None
patent: 10106269 (1998-04-01), None
patent: 10124484 (1998-05-01), None
patent: 10177520 (1998-06-01), None
patent: WO98/13759 (1998-04-01), None
Richard York; Real Time Debug for System-on-Chip Devices; Jun. 1999; pp. 1-6.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for selecting and using source operands in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for selecting and using source operands in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for selecting and using source operands in... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2901663

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.