Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-19
2002-11-26
Tran, M. (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06487703
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to computer software for the design of semiconductor chips. More particularly, it relates to a software method for analyzing inductive coupling noise in a circuit design.
BACKGROUND
In the field of circuit design, and in particular very large scale integration (VLSI) design, it is desirable to store a design in a computer memory so that the design can be analyzed and modified to ensure that it meets desired specifications. The VLSI design stored in memory may include data regarding each element in the design and about connections between elements. Parts of the design may include transmission lines or other connecting portions that connect the devices in the design.
These lines have certain circuit characteristics that may also be included in the design model. For example, the transmission lines may have a certain resistance and self-inductance. The transmission lines may also have coupling capacitance between adjacent lines, and between the line and ground, depending upon the circuit configuration. The properties of the lines may cause signal integrity problems when adjacent lines transition from low to high, or vice versa. Depending upon the line properties, an “aggressor” line physically close to a “victim” line may create noise on the victim line. Signal integrity is affected by the strength of the signals and the time required for signals to transition from low to high, or vice versa, referred to as the transition rate. In order to properly analyze the circuit, it is desirable to determine the capacitive coupling, the resistance, the transition rate, and the strength of the victim driver to ensure that the lines meet specification. Methods are known to exist for extracting each of these elements relatively quickly and easily.
Transmission lines also have a self-inductance, L, and physically close lines in a circuit design also have a mutual inductance, M. The mutual and self-inductance also affects signal performance and should be analyzed as part of the circuit analysis. Existing methods do not provide a quick and easy means for determining inductance. However, as designs continue to scale downward in size, inductance becomes a more significant factor in circuit performance. Also, as designs begin using copper and other materials with a lower resistivity, line resistance decreases, again making the inductance a more significant factor in the circuit analysis. What is needed is a method and system for easily and quickly estimating the inductance effects of lines in a VLSI design.
SUMMARY OF INVENTION
A method is disclosed for estimating the inductive coupling noise of a signal on a transmission line in a circuit design stored in a computer memory. The design may have a specification for a maximum amount of noise on a signal. The method determines the noise on the signal caused by capacitive coupling between lines, also referred to as the line capacitance. Noise caused by the inductive coupling is then added to the capacitive coupling noise to compute a total noise value, which is compared to the specification. The inductive coupling is a percentage of the supply voltage, which percentage varies depending upon the transition rate of the signal, the resistance of the line, and the gate capacitance of a load on the line.
The inductive coupling varies based on the circuit design and may be stored in a table having inductive coupling values for multiple design conditions. The table is created for a design by specifying initial conditions such as the width of the lines, the spacing between lines, the maximum distance to a ground line, and the transition rate of a signal on the line. A field solver may process these initial conditions to determine line characteristics for each line, such as resistance, capacitance, and inductance. A circuit simulation application then uses the characteristics to calculate the total noise on the lines as a percentage of supply voltage. The circuit simulation application also determines the RC noise on the lines caused by the resistance and capacitance, excluding the inductance. From these values, the method concludes that the difference in noise values is attributable to inductive coupling. For each line in the portion of the design considered, the method calculates the inductive coupling and records the maximum inductive coupling noise for any line within a specified portion, for example between regularly-spaced ground lines. For each set of initial conditions, a worst-case inductive coupling value is recorded in the table for use by the method.
In one embodiment, the method determines whether the inductive coupling causes noise in excess of four percent of the supply voltage. If the noise is less than four percent, it is ignored; otherwise, the inductive coupling noise is determined, added to the capacitive coupling noise, and compared to the total amount of noise. In one embodiment, the method assumes that ground signals are routed throughout the design at regular intervals to minimize the effect of inductive coupling.
REFERENCES:
patent: 6378109 (2002-04-01), Young et al.
Lin Shen
McBride John G.
Nakagawa Osamn S.
Hewlett--Packard Company
Tran M.
LandOfFree
Method and system for screening a VLSI design for inductive... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for screening a VLSI design for inductive..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for screening a VLSI design for inductive... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2939238