Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
1998-12-23
2002-07-09
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S501000, C710S021000, C710S045000, C710S060000
Reexamination Certificate
active
06418538
ABSTRACT:
FIELD
The present invention relates to the transfer of information in a computer system. More particularly, the present invention relates to a half duplex link protocol for isochronous transactions.
BACKGROUND
Information, such as information representing audio, video and multimedia content, can be transferred within a computer system. Consider, for example,
FIG. 1
, which illustrates a known architecture for connecting an external Input Output (IO) device
10
to a computer system
100
. The computer system
100
includes a processor
110
coupled to a main memory
200
through a memory controller
300
. The external IO device
10
communicates with an IO unit
400
, which is also coupled to the memory controller
300
.
The external IO device
10
can, for example, transfer “asynchronous” information with the IO unit
400
, which in turn transfers information with the memory controller
300
. When a transfer of information is asynchronous, delays can occur that interfere with the timely completion of the transfer. Typically, other, more important, activities can delay an information transfer without adversely impacting system performance. In some types of information streams, however, even a minor delay or gap will noticeably degrade the quality of the information, such as by causing a momentary freeze in a video transmission or by introducing a stuttering effect in an audio transmission.
When a transfer of information is “isochronous,” a sending and receiving device are partly synchronized, generally without using the same clock signal, and the sending device transfers information to the receiving device at regular intervals. Such transfers can be used, for example, when information needs to arrive at the receiving device at the same rate it is sent from the sending device, but without precise synchronization of each individual data item. The IEEE 1394 standard (1995), entitled “High Performance Serial Bus” and available from the Institute of Electrical and Electronic Engineers, is one example of an interface that supports the isochronous transfer of information.
In addition to the isochronous transfer of information between the external IO device
10
and the computer system
100
, the transfer of information within the computer system
100
may also be isochronous. U.S. patent application Ser. No. 09/110,344, entitled “Architecture for the Isochronous Transfer of Information Within a Computer System,” to John I. Gamey and Brent S. Baxter, filed on Jul. 6, 1998, discloses an architecture that provides for the isochronous transfer of information within a computer system.
In this case, the IO unit
400
may perform both isochronous and asynchronous information transfers, or “transactions,” with the memory controller
300
. In addition, the IO unit
400
may have several different transactions to be sent to (or received from) the memory controller
300
at substantially the same time. Similarly, the memory controller
300
may have several different transactions to be sent to (or received from) the IO unit
400
.
The connection
500
, or “link,” between the IO unit
400
and the memory controller
300
, however, is typically a “half duplex” link. A half duplex link between two devices is one that lets information be transferred in both directions, that is from the first to the second device and from the second to the first device, but not in both directions at the same time.
Because both the IO unit
400
and the memory controller
300
may each have information ready to be transferred over the half duplex link
500
, or “pending” transactions, particular transactions can be selected to be transferred across the link
500
, or “scheduled.” This scheduling can pose a number of problems.
For example, a memory “read request” transaction sent from the IO unit
400
to the memory controller
300
will result in a memory “read return” transaction from the memory controller
300
to the IO unit
400
, containing the requested data, at a later point in time. When the read return transaction is ready, however, another transaction, such as a memory “write” transaction from the IO unit
400
to the memory controller
300
may also be ready to be transferred across the half duplex link
500
. Because both transactions cannot be transferred across the half duplex link
500
simultaneously, some form of contention arbitration, priority scheme or flow control procedure is needed to resolve the access conflict.
These methods of resolving access conflicts on the half duplex link
500
may require one or more large data buffers, such as one or more First-In, First-Out (FIFO) data buffers, to store isochronous information when the half duplex link
500
cannot be accessed. In this case, information being transferred, for example, between the IO device
10
and the main memory
200
can be stored to, or retrieved from, various buffers when the half duplex link
500
is not available. This buffering can accommodate delays thereby reducing the gaps in an isochronous stream within the computer system
100
.
The contention arbitration and/or large data buffers can increase the cost, lower the performance and make the computer system
100
more difficult to build and test. Moreover, information within the computer system
100
may still not be transferred in a reliable and timely fashion if the delays are too long.
SUMMARY
In accordance with an embodiment of the present invention, transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. The transfer of a read request transaction, from the first device to the second device, is scheduled in one service period. The transfer of a write transaction, from the first device to the second device, is scheduled such that the write transaction will not be transferred across the half duplex link in the same service period as returning memory read data is transferred across the half duplex link.
In accordance with another embodiment of the present invention, transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. A first transaction associated with a first agent is scheduled in a first service period according to a global schedule. The global schedule associates the first service period with the first agent. A second transaction associated with a second agent is scheduled in a second service period according to the global schedule. The global schedule associates the second service period with the second agent.
REFERENCES:
patent: 5197125 (1993-03-01), Engel et al.
patent: 5386435 (1995-01-01), Cooper
patent: 5504900 (1996-04-01), Raz
patent: 5513368 (1996-04-01), Garcia et al.
patent: 5521926 (1996-05-01), Ayerst et al.
patent: 5533200 (1996-07-01), Dobbins et al.
patent: 5546543 (1996-08-01), Yang et al.
patent: 5619361 (1997-04-01), Sagesaka et al.
patent: 5898666 (1999-04-01), Fukuda
patent: 5898848 (1999-04-01), Gulick
patent: 5961623 (1999-10-01), James et al.
patent: 6067591 (2000-05-01), Howard et al.
Baxter Brent S.
Garney John I.
Gaffin Jeffrey
Kenyon & Kenyon
Mai Rijue
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