Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-09-03
2004-04-06
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S023000, C714S051000, C714S055000, C714S056000, C710S110000
Reexamination Certificate
active
06718488
ABSTRACT:
BACKGROUND
1. Technical Field
This patent application relates, in general, to information processing systems and, in particular, to a method and system for responding to a failed bus operation in an information processing system.
2. Description of the Related Art
Various information processing systems manipulate, process, and store information. Personal computer systems, and their associated subsystems are examples of information processing systems.
Personal computer systems typically include a motherboard for mounting at least one microprocessor and other application specific integrated circuits (ASICs), such as memory controllers and input/output (I/O) controllers. Many motherboards include slots for additional adapter cards to provide additional function to the computer system. Typical functions that a user might add to a computer include additional microprocessors, additional memory, fax/modem capability, sound cards, or graphics cards. The slots included on the motherboard generally include in-line electrical connectors having electrically conductive lands which receive exposed tabs on the adapter cards. The lands are connected to wiring layers, which in turn are connected to a bus that allows the cards to communicate with the microprocessor or other components in the system.
A personal computer system may include many different types of buses to link the various components of the system. One type of bus is a “master-slave” bus, which refers to a bus architecture in which, during any transaction involving the bus, a bus device (the master) controls one or more other devices (the slaves). One example of a master-slave bus is the I
2
C (Inter-Integrated Circuit (IC)) bus, which is used to connect integrated circuits. I
2
C is a multi-master bus, so that multiple chips can be connected to the same bus and each one can act as a master by initiating an information (e.g. data and/or address) transfer. Another example of a master-slave bus is the System Management Bus (SMBUS). The SMBUS is a master-slave bus through which simple power-related chips can communicate with the rest of an information processing system.
Personal computer systems often use internal busses such as the I
2
C Bus, SMBUS, or other expansion busses to initialize and interrogate devices (e.g., memory components, environmental probes, clock synthesizers). These devices may exist on the same bus as interchangeable master or slave devices and operate using similar master-slave protocols.
The I
2
C Bus physically consists of 2 active wires and a ground connection. The active wires are Serial DAta line (SDA) and the Serial CLock line (SCL). Both active wires (SDA and SCL) are bi-directional.
An integrated circuit hooked on the I
2
C Bus may have its own unique address. For example, the integrated circuit may be a memory component, environmental probe, or clock synthesizer. These integrated circuits can act as a receiver and/or transmitter depending on their functionality.
Because the SDA is a serial line, an I
2
C Bus slave device retains control of the I
2
C Bus long enough for the slave device to complete its tasks and serially transmit the information appropriate to the slave device's task back over the SDA to its master. This is accomplished by the slave device holding the SCL low. After the device has finished transmitting, the slave device toggles the SCL high, which tells the master that the slave has completed its task and that the master can resume its functioning.
Typically, each I
2
C Bus device operating under a master-slave protocol contains an internal state machine that handles the protocols related to toggling the SCL. However, it has been discovered that, if a cycle is interrupted, or a timing parameter is not met correctly, the state machine of the slave device can enter an erroneous state wherein the slave device may fail to toggle the SCL line. Accordingly, the master might fail to resume processing, thereby locking the I
2
C Bus and making use of the I
2
C Bus impractical.
The forgoing has described the “locking” of an I
2
C Bus arising from the malfunctioning of a state machine at a slave device. However, those skilled in the art will recognize that similar problems can also arise in the functioning of SMBUS, which typically uses an I
2
C Bus as its backbone.
Those skilled in the art will recognize that the locking of an I
2
C Bus or an SMBUS, if it occurs very early in the initialization of an information processing system, might manifest as the system not detecting any memory and stopping prior to video being initialized which would prevent visible feedback of the problem (e.g., the display could present the problem with the system, but if the defect stops the video from being initialized, the system is unusable, and a human user has no indication of why the system is not functioning). Those skilled in the art will also recognize that the locking of an I
2
C Bus or an SMBUS, should it occur somewhat later in the initialization of an information processing system, might manifest as the loss of environmental probes which would prevent the system from properly handling over-temperature conditions. Those skilled in the art will recognize that the foregoing-described manifestations of the locking of an I
2
C Bus or an SMBUS are merely examples, and that the locking of an I
2
C Bus or an SMBUS can manifest in many different ways.
Many devices that reside on an I
2
C Bus or an SMBUS are designed with minimal pin count packages. Accordingly, when an I
2
C Bus or an SMBUS becomes “locked” due to state machine malfunction, it might be necessary to change the power pin (Vcc) in order to reset the malfunctioning devices' internal state machine and thereby regain use of the bus.
Accordingly, a need exists in the art for detecting and remedying a locked master-slave bus, such as the I
2
C Bus or the SMBUS bus.
SUMMARY
In an information processing system, a failed bus operation is detected. In response to the detecting, a primary power plan is cycled in the information processing system.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of this patent application will become apparent in the non-limiting detailed description set forth below.
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Tanenbaum, Andrew S., Structured Computer Organization, 1990, Prentice Hall, Inc., pp. 11-13.*
Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub Datasheet, Jun. 1999, sections 8.8.3.1-8.8.3.16 and 8.9.1-8.9.11.*
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The I2C-Bus Specification(Version 2.0 Dec. 1998), available from Philips Semiconductor, Inc.
82371AB PCI ISA IDE Xcelerator(PIIX4) specification, Section 11.5.4, available from Intel Corporation.
System Management Bus Specification(Revision 1.1 Dec. 11, 1998), available from Benchmarq Microelectronics, Inc.
Jue Stephen D.
Martin Todd R.
Baderman Scott
Baker & Botts L.L.P.
Dell USA L.P.
Maskulinski Michael
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