Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-28
2010-06-01
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07730432
ABSTRACT:
The present invention provides a method and system for designing an integrated circuit (IC). The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method achieves a target objective of a transistor, of a cell, or of part of or the entire IC. The method of designing the IC includes reshaping a basic shape of the transistor. The method includes determining a reshaping bias solution of the transistor. The method further includes modifying the basic shape of the transistor channel, based on the reshaping bias solution, and preparing a reshaped layout design.
REFERENCES:
patent: 5424985 (1995-06-01), McClure et al.
patent: 6091845 (2000-07-01), Pierrat et al.
patent: 6297668 (2001-10-01), Schober
patent: 6306710 (2001-10-01), Long et al.
patent: 6566710 (2003-05-01), Strachan et al.
patent: 6928635 (2005-08-01), Pramanik et al.
patent: 6931617 (2005-08-01), Sanie et al.
patent: 6954918 (2005-10-01), Houston
patent: 6968527 (2005-11-01), Pierrat et al.
patent: 6993741 (2006-01-01), Liebmann et al.
patent: 7149999 (2006-12-01), Kahng et al.
patent: 7175940 (2007-02-01), Laidig et al.
patent: 7222328 (2007-05-01), Hasumi et al.
patent: 7441211 (2008-10-01), Gupta et al.
patent: 7487475 (2009-02-01), Kriplani et al.
patent: 7523429 (2009-04-01), Kroyan et al.
patent: 2003/0212966 (2003-11-01), Cadouri
patent: 2003/0229881 (2003-12-01), White et al.
patent: 2005/0186746 (2005-08-01), Lee et al.
patent: 2006/0101370 (2006-05-01), Cui et al.
patent: 2006/0150132 (2006-07-01), Gupta
patent: 2007/0150847 (2007-06-01), Ikeda
patent: 2007/0234252 (2007-10-01), Visweswariah et al.
patent: 2008/0046846 (2008-02-01), Chew et al.
patent: 2008/0127029 (2008-05-01), Graur et al.
patent: 2008/0148216 (2008-06-01), Chan et al.
patent: 2009/0024974 (2009-01-01), Yamada
patent: 2009/0055788 (2009-02-01), Cote et al.
patent: 2009/0077524 (2009-03-01), Nagamura et al.
patent: 2009/0106714 (2009-04-01), Culp et al.
patent: 2002-258463 (2002-09-01), None
Sreedhar, A. Kundu, S. “Statistical Yield Modeling for Sub-wavelength Lithography”, Dept. of Electr. & Comput. Eng., Univ of Massachusetts at Amherst, Amherst, MA This paper appears in: Test Conference, 2008, ITC 2008. IEEE International Publication Date: Oct. 28-30, 2008, pp. 1-8.
Puneet Gupta, UC San Diego, La Jolla; Andrew B. Kahng, UC San Diego, La Jolla, “Manufacturing-Aware Physical Design”, International Conference on Computer Aided Design archive; Proceedings of the 2003 IEEE/ACM International conference on Computer-aided design table of contents p. 681; Year of Publication: 2003; Publisher: IEEE Computer Society Washington, DC, USA.
Axelrad, V. Cobb, N. O'Brien, M. Boksha, V. Do, T. Donnelly, T. Granik, Y. Sahouria, E. Balasinski, A.; Sequoia Design Syst., Woodside, CA; “Efficient full-chip yield analysis methodology for OPC-corrected VLSI designs”, This paper appears in: Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on Publication Date: 2000; pp. 461-466, San Jose, CA, USA.
“Manufacturing-aware design helps boost IC yield”; Website: http://www.eetimes,com
ews/design/features/showArticle.jhtml?articleID=47102054; Publication date: Sep. 9, 2004.
Gupta P. et al., “Joining the Design and Mask Flows for Better and Cheaper Masks,” Proc. 24thBACUS Symposium on Photomask Technology and Management, Sep. 2004, 12 pages.
Gupta P. et al., “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control,” DAC 2004, Jun. 7-11, 2004, pp. 327-330, San Diego, CA.
Clark L. et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design”, Proceedings IEEE International Symposium on Low Power Electronic Design, 2004, pp. 275-279.
Gupta Puneet
Kahng Andrew
Reed Dave
Do Thuan
Martine & Penilla & Gencarella LLP
Tela Innovations, Inc.
LandOfFree
Method and system for reshaping a transistor gate in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for reshaping a transistor gate in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for reshaping a transistor gate in an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4168055