Method and system for reliably indicating test results during a

Details Method and system for reliably indicating test results during a Method and system for reliably indicating test results during a

1998-09-21

2000-07-04

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 36, 714 40, G06F 1127

Patent

active

060853379

ABSTRACT:
A method and system for accurately indicating test results from testing routines of a self-check operation during initialization or reset of the system utilize test result bits in a secure status register that must be sequentially reset to indicate a successful completion of the self-check operation. The system is a microcontroller that can be incorporated into various consumer products requiring digital processing. Each test result bit represents a distinct component of the system that is tested during the self-check operation. The test result bits in the status register can only be reset one at a time, by activating a demultiplexer which resets a particular test result bit in response to a successful testing of a component. However, the demultiplexer can only be activated by modifying a control bit in an access register that is protected by a double password scheme. To modify the control bit, the CPU must provide two valid passwords. The activation of the demultiplexer is repeated for each component of the system that is tested to reset a corresponding test result bit in the status register. Consequently, the CPU must write a different device designation value into the control register for each component that is tested. When all the test result bits have been reset, a confirmation signal is generated.

REFERENCES:
patent: 4726024 (1988-02-01), Guziak et al.
patent: 5640509 (1997-06-01), Balmer et al.
patent: 5704038 (1997-12-01), Mueller et al.
patent: 5974240 (1999-10-01), Chan

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