Method and system for reducing volatile DRAM power budget

Details Method and system for reducing volatile DRAM power budget Method and system for reducing volatile DRAM power budget

2005-02-25

2008-05-27

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S200000

Reexamination Certificate

active

07379368

ABSTRACT:
A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.

REFERENCES:
patent: 6510394 (2003-01-01), Huang et al.
patent: 7024571 (2006-04-01), Reger et al.
patent: 7139937 (2006-11-01), Kilbourne et al.

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