Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2000-06-21
2004-01-20
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C716S030000, C711S105000
Reexamination Certificate
active
06681338
ABSTRACT:
TECHNICAL FIELD
This invention relates to skew-reducing systems and methods and, more particularly, concerns skew-reducing systems and methods for use in connection with In-line Memory Modules (IMMs), such as the RIMM® systems of Rambus Inc. (a corporation having a place of business in California).
BACKGROUND
As computer processors increase in speed they require increased information bandwidth from other subsystems supporting the processor. An example is the large amount of bandwidth needed by video and 3D image processing from a computer memory subsystem. Another example is a main memory subsystem. One or more high frequency buses are typically employed to provide the bandwidth required. The higher the frequency of operation of the bus, the greater the requirement that the signals on the bus have high-fidelity and equal propagation times to the devices making up the subsystem. High-fidelity signals are signals having little or no ringing and controlled and steady rising and falling edge rates. Many obstacles are encountered in assuring the uniform arrival times of high-fidelity signals to devices on the bus. One such obstacle is a requirement that a subsystem be modular, meaning that portions of a subsystem may be added and possibly removed. The modularity requirement implies that devices that are part of the modular subsystem be mounted on a separate substrate or module which couples to another board, the motherboard. It also implies the use of connectors if both addition and removal is required. Other obstacles are the number of layers of the motherboard on which routing of the bus is allowed and whether the bus is routed in a straight line or routed with turns. Too few layers on a motherboard, or a module, and turns of the lines may not permit the construction of the bus lines in a way necessary to achieve uniform arrival times of high-fidelity signals to devices on the bus.
Modular subsystems in computers have numerous advantages, some of which are field upgradability, replacement of a failing device, flexibility of initial configuration, and increased device density. Currently, so called DIMMs (dual in-line memory modules) and Rambus in-line memory modules (i.e. RIMM® systems) are examples of computer memory systems employing such modules. Because of these advantages and the desirability of having high performance modular memory subsystems, it is especially important to have buses with uniform arrival times to devices in applications where modules are employed.
A problem with such modules is that signal propagation delays can become introduced in the modules because of the nature of the material through which the signals are routed. More specifically, a typical module comprises a multi-layer circuit board structure with various conductive lines extending through the module separated by one or more dielectric material layers. High speed signals are typically propagated through the conductive lines to various devices that are located on the module. Because of variations in the dielectric properties of the dielectric material layer(s), however, signals that are desired to have no meaningful propagation delay differences are found to have undesirable propagation delay differences. This, in turn, can adversely affect compliance with timing budgets.
Accordingly, this invention arose out of concerns associated with providing improved systems and methods of using and forming such systems that have desirably minimal signal propagation delay differences.
SUMMARY
Methods and systems for reducing signal skew caused by dielectric material variations within one or more module substrates are described. In one embodiment, an elongate module substrate having a long axis includes multiple signal routing layers supported by the module substrate. Multiple devices, such as memory devices (e.g. DRAMs) are supported by the module substrate and are operably connected with the signal routing layers. Multiple skew-reducing locations (e.g. vias) within the module permit signals that are routed in two or more of the multiple signal routing layers to be switched to a different signal routing layer. The skew-reducing locations can be arranged in at least one line that is generally transverse the long axis of the module substrate. The lines of skew-reducing locations can be disposed at various locations on the module. For example, a line of skew-reducing locations can be disposed proximate the middle of the module to effectively offset skew. Multiple skew-reducing locations can be provided at other locations within the module as well so that the signals are switched multiple different times as they propagate through the module.
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Technical Note TN1138, “High-Speed SDRAM Design Considerations,” http://developer.apple.com/technotes/tn/pdf/tn1138.pdf, Aug. 31, 1998.
Chang Eric
Lee Thomas
Lee & Hayes PLLC
Rambus Inc.
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