Method and system for reducing memory access latency by providin

Details Method and system for reducing memory access latency by providin Method and system for reducing memory access latency by providin

1997-03-05

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

364DIG1, 3642434, 365 49, 36518533, 711 5, 711118, 711205, G06F 1200

Patent

active

058025545

ABSTRACT:
A system and method for reducing access latency to stable storage are described. A technique referred to as fault trickling is used to improve access latency to stable storage such as flash memory. In particular, data requests from a central processing unit are preferentially satisfied by a memory management unit providing access to a main memory. When the requested data does not reside in the main memory, however, the memory management unit satisfies the request by providing direct fine-grain access to the flash memory. In addition, concurrently with satisfying the data request directly from the flash memory, a block transfer is initiated from the flash memory to the main memory. Once the block transfer is completed, a memory map, such as an address translation table, is updated to indicate that the data now resides in the more convenient source of data--the main memory. Accordingly, subsequent data requests, for that or proximately located data, can be satisfied by accessing the main memory.

REFERENCES:
patent: 3896419 (1975-07-01), Lange et al.
patent: 4056845 (1977-11-01), Churchill, Jr.
patent: 4169284 (1979-09-01), Hogan et al.
patent: 4467419 (1984-08-01), Wakai
patent: 4835678 (1989-05-01), Kofuji
patent: 4912636 (1990-03-01), Magar et al.
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 5073851 (1991-12-01), Masterson et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5185875 (1993-02-01), Chinnaswamy et al.
patent: 5196772 (1993-03-01), Bergendahl et al.
patent: 5276845 (1994-01-01), Takayama
patent: 5283883 (1994-02-01), Mishler
patent: 5293597 (1994-03-01), Jensen et al.
patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5293609 (1994-03-01), Shih et al.
patent: 5311462 (1994-05-01), Wells
patent: 5353256 (1994-10-01), Fandrich et al.
patent: 5369754 (1994-11-01), Fandrich et al.
patent: 5386552 (1995-01-01), Garney
patent: 5530673 (1996-06-01), Tobita et al.

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