Method and system for reducing latency

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S167000, C709S212000

Reexamination Certificate

active

07472234

ABSTRACT:
Embodiments generally relate to a method of reducing latency and cost. A device access request is received in a memory of non-local node over a NUMA interconnect from a source node. The device access request is forwarded to an off-node controller from the memory of the non-local node. The device access request completion notification and data is forwarded to the source node.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for reducing latency does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for reducing latency, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for reducing latency will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4035072

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.